JAJSLD1C May 2021 – November 2022 DLPC6540
PRODUCTION DATA
PARAMETER(1) | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
fclock | Source clock frequency | 40 (1 lane) 20 (1 lane with Pixel Repeat) (2) | 600 (8 lanes) | MHz | |
flink-ck | Link clock frequency per lane (3) | 8 lanes 4 lanes 2 lanes 1 lane | 43 43 43 43 (21.5 with Pixel Repeat) | 75 85 85 85 | MHz |
flink | Link transfer rate (3) | 3-Byte Mode 4-Byte Mode 5-Byte Mode | 2 2 2.15 | 2.55 3.0 3.0 | Gbps |
tRBIT | Unit interval | 3-Byte Mode 4-Byte Mode 5-Byte Mode | 392 294 294 | 500 500 500 | ps ps ps |
tA | Jitter Margin | 0.25 | UI | ||
tB | Rise / Fall Time | 0.05 | UI | ||
tEYE | Differential Data Eye | 0.5 | UI | ||
tskew_intra | Allowable intra-pair skew | 0.3 | UI | ||
tskew_inter | Allowable Inter-pair Skew | 5 | UI | ||
foskew_inter | Allowable inter-pair frequency offset | –300 | 300 | ppm | |
Tj | Total jitter | — | 0.5 | UI | |
Rj | Random jitter | 10^12 UI | - | 0.2 | UI |
Dj_ISI | Deterministic jitter (ISI) | - | 0.2 | UI | |
Sj | Sinusoidal jitter | - | 0.1 | UI |