JAJSLD1C May 2021 – November 2022 DLPC6540
PRODUCTION DATA
The DLPC6540 V-by-One SERDES differential interface waveform quality and timing is dependent on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many factors.
DLPC6540 I/O timing parameters, V-by-One transmitter timing parameters, as well as Thine specific timing requirements can be found in their corresponding data sheets. PCB routing mismatch can be budgeted and met through controlled PCB routing. PCB related requirements for V-by-One are provided in Table 9-5 as a starting point for the customer.
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
Intra-lane cross-talk (between VX1_DATAx_P and VX1_DATAx_N) | < 1.5 | mVpp | |||
Inter-lane cross-talk (between data lane pairs) | < 1.5 | mVpp | |||
Cross-talk between data lanes and other signals | < 1.5 | mVpp | |||
Intra-lane skew | < 40 | ps | |||
Inter-lane skew | < 5 | UI | |||
Differential Impedance | 90 | 100 | 110 | Ω |
Additional V-by-One layout guidelines: