JAJSH15H October   2014  – June 2024 DLPC900

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  System Oscillators Timing Requirements #GUID-909D0FD3-84C7-4481-924A-4FDE7EB548A1/DLPS0373944
    7. 5.7  Power-Up and Power-Down Timing Requirements
      1. 5.7.1 Power-Up
      2. 5.7.2 Power-Down
    8. 5.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 5.9  JTAG Interface: I/O Boundary Scan Application Switching Characteristics
    10. 5.10 Programmable Output Clocks Switching Characteristics
    11. 5.11 Port 1 and 2 Input Pixel Interface Timing Requirements
    12. 5.12 Two Pixels Per Clock (48-Bit Bus) Timing Requirements
    13. 5.13 Synchronous Serial Port (SSP) Switching Characteristics
    14. 5.14 DMD Interface Switching Characteristics
    15. 5.15 DMD LVDS Interface Switching Characteristics
    16. 5.16 Source Input Blanking Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DMD Configurations
      2. 6.3.2 Video Timing Input Blanking Specification
      3. 6.3.3 Board-Level Test Support
      4. 6.3.4 Two Controller Considerations
      5. 6.3.5 Memory Design Considerations
        1. 6.3.5.1 Flash Memory Optimization
        2. 6.3.5.2 Operating Modes
        3. 6.3.5.3 DLPC900 External Memory Space
        4. 6.3.5.4 Minimizing Memory Space
        5. 6.3.5.5 Minimizing Board Size
          1. 6.3.5.5.1 Package Selection
          2. 6.3.5.5.2 Large Density Flash
            1. 6.3.5.5.2.1 Combining Two Chip-Selects with One 32-Megabyte Flash
            2. 6.3.5.5.2.2 Combining Three Chip-Selects with One 64-Megabyte Flash
            3. 6.3.5.5.2.3 Combining Three Chip-Selects with One 128-Megabyte Flash
        6. 6.3.5.6 Minimizing Board Space
        7. 6.3.5.7 Flash Memory
    4. 6.4 Device Functional Modes
      1. 6.4.1 Structured Light Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Two Controller Chipset
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 DLPC900 System Interfaces
            1. 7.2.1.2.1.1 Control Interface
            2. 7.2.1.2.1.2 Input Data Interfaces
            3. 7.2.1.2.1.3 DLPC900 System Output Interfaces
              1. 7.2.1.2.1.3.1 Illumination Interface
              2. 7.2.1.2.1.3.2 Trigger and Sync Interface
            4. 7.2.1.2.1.4 DLPC900 System Support Interfaces
              1. 7.2.1.2.1.4.1 Reference Clock and PLL
              2. 7.2.1.2.1.4.2 Program Memory Flash Interface
              3. 7.2.1.2.1.4.3 DMD Interface
      2. 7.2.2 Typical Single Controller Chipset
  9. 8 Power Supply Recommendations
    1. 8.1 System Power Regulation
      1. 8.1.1 Power Distribution System
        1. 8.1.1.1 1.15V System Power
        2. 8.1.1.2 1.8V System Power
        3. 8.1.1.3 3.3-V System Power
    2. 8.2 System Environment and Defaults
      1. 8.2.1 DLPC900 System Power-Up and Reset Default Conditions
    3. 8.3 System Power-Up Sequence
      1. 8.3.1 Power-On Sense (POSENSE) Support
      2. 8.3.2 Power Good (PWRGOOD) Support
      3. 8.3.3 5V Tolerant Support
    4. 8.4 System Reset Operation
      1. 8.4.1 Power-Up Reset Operation
      2. 8.4.2 System Reset Operation
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  General PCB Recommendations
      2. 9.1.2  PCB Layout Guidelines for Internal Controller PLL Power
      3. 9.1.3  PCB Layout Guidelines for Quality Video Performance
      4. 9.1.4  Recommended MOSC Crystal Oscillator Configuration
      5. 9.1.5  Spread Spectrum Clock Generator Support
      6. 9.1.6  GPIO Interface
      7. 9.1.7  General Handling Guidelines for Unused CMOS-Type Pins
      8. 9.1.8  DMD Interface Considerations
        1. 9.1.8.1 Flex Connector Plating
      9. 9.1.9  PCB Design Standards
      10. 9.1.10 Signal Layers
      11. 9.1.11 Trace Widths and Minimum Spacing
      12. 9.1.12 Trace Impedance and Routing Priority
      13. 9.1.13 Power and Ground Planes
      14. 9.1.14 Power Vias
      15. 9.1.15 Decoupling
      16. 9.1.16 Fiducials
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
      2. 10.1.2 Device Markings
      3. 10.1.3 DEFINITIONS—Video Timing Parameters
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Revision History

Changes from Revision G (November 2023) to Revision H (June 2024)

  • DRAM メモリに保存できる 1 ビット パターンの数を更新Go
  • Updated the number of 1-bit pre-stored patterns for each DMD in Table 6-3 Go
  • Updated the DLP5500 DMD minimum pattern time for bit depth 3 and 6 in Table 6-4 Go
  • Added pattern speed examples with dark time in Table 6-5 Go
  • Added mimimum exposure time for active block 16 (DLP5500) and active block 6 (DLP670S) in Table 6-6 Go

Changes from Revision F (June 2021) to Revision G (November 2023)

  • 一覧を再編成し、サポート対象デバイスの一覧に DLP5500 DMD を追加Go
  • 高速パターン速度の表現を編集し、DLP500YX に関する明確な情報を追加Go
  • フラッシュ メモリで保持できるパターンの数を削除Go
  • 「ビデオ モード」セクションの SVGA を XGA に訂正Go
  • DLPC900 コントローラでサポートされるデバイスのリストに DLP5500 DMD を追加Go
  • TI.com に掲載されなくなったページへのリンクを削除Go
  • アプリケーション概略図からファン ブロックを削除Go
  • DLP5500500 と他のすべての DMD で利用可能な 1 ビット パターンの数を列挙Go
  • Moved placement of footnote 3 in the Trigger Control Pin Function table Go
  • Moved pins H23 and G23 from the Reserved Pin Functions table to Port1 and Port2 Channel Data and Control Pin Functions table.Go
  • Moved pins E8, B4, C4, E7, D5, E6, D3, C2, A4, B5, C6, A5, and D7 from Reserved Pin Functions table to Board-Level Test and Debug Pin Functions tableGo
  • Moved pins AD8, AE8, AF9, G24, D26, F23, F22, E24, and D25 from the Reserved Pin Functions table to the Peripheral Interface Pin Functions tableGo
  • Removed extraneous YCbCr referenceGo
  • Added the tSB parameter to Table 5-1 tableGo
  • Removed tEW from Table 5-1 table - duplicates tPH Go
  • Added DLPA200 to Figure 5-3 Go
  • PWRGOOD cannot be uses as an early warning signal for an anticipated power down.Go
  • Changed Power Mode = 1 "Standby" instructions for anticipated power down.Go
  • Changed Anticipated Power Down Sequence and Unanticipated Power Down Sequence diagrams to match the behavior of the DLPC900 controller.Go
  • Added DLP5500 DMD to list of supported devicesGo
  • Added XGA resolution to single DLPC900 controller systems for the DLP5500Go
  • Changed phrasing from 'normal' to 'default'Go
  • Changed the section name from DLPC900 Memory Space to DLPC900 External Memory SpaceGo
  • Updated GPIO signal namesGo
  • Updated GPIO signal namesGo
  • Removed lists of flash memory components and added links to the appropriate BOMs on TI.com Go
  • Added information about the number of 1-bit patterns the DLP5500 can pre-load and corrected the 1-bit depth of the DLP670S DMDGo
  • Added information to the tables about minimum exposure times for the DLP5500Go
  • Added table listing the number of 1-bit pre-stored patterns for each DMDGo
  • Updated Section to include DLP5500 DMD and reordered the DMD names.Go
  • Updated block diagram and added Table 7-1 Go
  • Updated DMD interface lists to include support for the DLP5500Go
  • Corrected P1_ bits to [0:9]Go
  • Added information about optional GPIOs for extended external memory accessGo
  • Updated the schematic to reflect the DLP5500Go
  • Updated Related Documents Table (added DLPLCR55EVM)Go