JAJST20 March 2024 DLPC964
PRODUCTION DATA
After power is applied to the DLPC964, the APPS FPGA monitors the DONE_0 signal to determine when the DLPC964 completed configuration. The APPS FPGA next monitors the INIT_DONE signal to determine when the DLPC964 completed its internal initialization routines and configured the DMD for normal operation. An alternate method is to request the initialization status using the I2C interface. Information regarding initialization, versions, and IDs can be requested through this interface.
To define the start of a DMD block, the APPS FPGA must send a Block Control Word packet through the HSS Channel 0 input to the DLPC964. Control word packets sent over Aurora 64B/66B Channels 1, 2, and 3 are not used and are ignored by the DLPC964 controller. After the Block Control Word is sent to the DLPC964 controller, the APPS FPGA can begin loading data across all four Aurora 64B/66B Channels to the DLPC964 controller. Once the data transfer is complete on all four Aurora 64B/66B Channels, the APPS FPGA must assert DMDLOAD_REQ to signal the DLPC964 controller the end of a DMD block, and trigger it to carry out the operation encoded in the Block Control Word. While the DLPC964 controller is carrying out the operation encoded in the Block Control Word, it asserts the BLKLOADZ signal. Once the BLKLOADZ signal is deasserted, the APPS FPGA is free to send the next Block Control Word packet to the DLPC964 controller.
During the Block Control Word packet and subsequent data loading across all four Aurora 64B/66B Channels, the APPS FPGA should set up the BLKADDR and BLKMODE signals for the desired MCP operation. Once the DLPC964 deasserts the BLKLOADZ signal, and data loading operations are complete for the desired DMD block, MCP_START can be asserted to begin the desired MCP operation and display the loaded data on the DMD mirrors. While a MCP_START operation is in progress, the DLPC964 asserts MCP_ACTIVE to signal to the APPS FPGA that a MCP mirror operation is currently in progress.