JAJST20 March 2024 DLPC964
PRODUCTION DATA
The APPS FPGA user logic can assert the DMDLOAD_REQ signal as soon as the Aurora block data transfer is complete, as long as it is at least 300ns after sending the first data packet of that block data transfer. This setup time requirement is due to the 300ns transmit latency of the Aurora TX/RX channel paths, and guarantees the DLPC964 Controller will receive the DMDLOAD_REQ flag after the arrival of Aurora block data transfer.
In most cases, this 300ns setup requirement is naturally met due to the size of a data block transfer. It is large enough to guarantee well over 300ns from the first valid data packet being sent to the last ones of a block when the APPS FPGA can assert the DMDLOAD_REQ signal. The 300ns setup window becomes critical when the APPS FPGA attempts to send a small partial DMD data block such as in Figure 7-7, showing an example of the APPS FPGA sending a total of just 3 rows (Table 7-3, ROW_LENGTH = 3) of a DMD partial data block to the DLPC964 Controller:
APPS FPGA transmits a Block Control Word to indicate the start of an Aurora block data transfer.
After sending 3 rows of data through the four Aurora data interface channels, the APPS FPGA waits for the 300ns setup time to expire before issuing a DMDLOAD_REQ. Note, 300ns is measured from the start of the first TVALID on the data interface.
Once the setup time has been met, the APPS FPGA asserts DMDLOAD_REQ.
BLKLOADZ is asserted by the DLPC964 Controller, indicating a DMD data load operation is in progress.
For operations that do not require a data packet, such as block-clear (Table 7-3, LOAD_TYPE = 001) and block-set (Table 7-3, LOAD_TYPE = 010), the 300ns setup time for DMDLOAD_REQ is still required and is measured from the Block Control Word packet. An example of block-set operation is described in Figure 7-8: