JAJSEV0G july 2016 – august 2023 DP83822H , DP83822HF , DP83822I , DP83822IF
PRODUCTION DATA
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PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
T1 | AVD (analog
supply) ramp delay post VDDIO (digital supply) ramp. AVD and VDDIO potential must not exceed 0.3 V prior to supply ramp.(3) | Time from start of supply ramp | –100 | 100 | ms | |
VDDIO ramp time | 100 | ms | ||||
AVD ramp time | 100 | ms | ||||
T2 | Post power-up stabilization time prior to MDC preamble for register accesses. MDC preamble coming in any time after this max wait time will be valid. | MDIO is pulled high for 32-bit serial management initialization | 200 | ms | ||
T3 | Hardware configuration latch-in time for power up | 200 | ms | |||
T4 | Hardware configuration pins transition to output drivers | 64 | ns | |||
T5 | Fast Link Pulse transmission delay post power up | 1.5 | s |