8.6.67 DSP_CFG_25 Register (Offset = 0x33C) [reset = 0xEC00]
DSP_CFG_25 is shown in Table 79.
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Table 79. DSP_CFG_25 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15-8 |
deq_coeff_1 |
|
0xEC |
Reserved
|
7 |
RESERVED |
R |
0x0 |
Reserved
|
6-0 |
cfg_deq_coeff_force |
R/W |
0x0 |
EQUALIZATION_FRC_CTRL REGISTER
|