JAJSGP5A December 2018 – August 2019 DP83825I
PRODUCTION DATA.
Table 11 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 11 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0x0 | BMCR_Register | Go | |
0x1 | BMSR_Register | Go | |
0x2 | PHYIDR1_Register | Go | |
0x3 | PHYIDR2_Register | Go | |
0x4 | ANAR_Register | Go | |
0x5 | ALNPAR_Register | Go | |
0x6 | ANER_Register | Go | |
0x7 | ANNPTR_Register | Go | |
0x8 | ANLNPTR_Register | Go | |
0x9 | CR1_Register | Go | |
0xA | CR2_Register | Go | |
0xB | CR3_Register | Go | |
0xC | Register_12 | Go | |
0xD | REGCR_Register | Go | |
0xE | ADDAR_Register | Go | |
0xF | FLDS_Register | Go | |
0x10 | PHYSTS_Register | Go | |
0x11 | PHYSCR_Register | Go | |
0x12 | MISR1_Register | Go | |
0x13 | MISR2_Register | Go | |
0x14 | FCSCR_Register | Go | |
0x15 | RECR_Register | Go | |
0x16 | BISCR_Register | Go | |
0x17 | RCSR_Register | Go | |
0x18 | LEDCR_Register | Go | |
0x19 | PHYCR_Register | Go | |
0x1A | 10BTSCR_Register | Go | |
0x1B | BICSR1_Register | Go | |
0x1C | BICSR2_Register | Go | |
0x1E | CDCR_Register | Go | |
0x1F | PHYRCR_Register | Go | |
0x25 | MLEDCR_Register | Go | |
0x27 | COMPT_Regsiter | Go | |
0x101 | Register_101 | Go | |
0x10A | Register_10a | Go | |
0x123 | Register_123 | Go | |
0x130 | Register_130 | Go | |
0x170 | CDSCR_Register | Go | |
0x171 | CDSCR2_Register | Go | |
0x172 | TDR_172_Register | Go | |
0x173 | CDSCR3_Register | Go | |
0x174 | TDR_174_Register | Go | |
0x175 | TDR_175_Register | Go | |
0x176 | TDR_176_Register | Go | |
0x177 | CDSCR4_Register | Go | |
0x178 | TDR_178_Register | Go | |
0x180 | CDLRR1_Register | Go | |
0x181 | CDLRR2_Register | Go | |
0x182 | CDLRR3_Register | Go | |
0x183 | CDLRR4_Register | Go | |
0x184 | CDLRR5_Register | Go | |
0x185 | CDLAR1_Register | Go | |
0x186 | CDLAR2_Register | Go | |
0x187 | CDLAR3_Register | Go | |
0x188 | CDLAR4_Register | Go | |
0x189 | CDLAR5_Register | Go | |
0x18A | CDLAR6_Register | Go | |
0x302 | IO_CFG_Register | Go | |
0x308 | SPARE_OUT | Go | |
0x30B | DAC_CFG_0 | Go | |
0x30C | DAC_CFG_1 | Go | |
0x30F | DSP_CFG_0 | Go | |
0x311 | DSP_CFG_2 | Go | |
0x313 | DSP_CFG_4 | Go | |
0x31C | DSP_CFG_13 | Go | |
0x31F | DSP_CFG_16 | Go | |
0x33C | DSP_CFG_25 | Go | |
0x33E | DSP_CFG_27 | Go | |
0x404 | ANA_LD_PROG_SL_Register | Go | |
0x40D | ANA_RX10BT_CTRL_Register | Go | |
0x416 | Register_416 | Go | |
0x429 | Register_429 | Go | |
0x456 | GENCFG_Register | Go | |
0x460 | LEDCFG_Register | Go | |
0x461 | IOCTRL_Register | Go | |
0x467 | SOR1_Register | Go | |
0x468 | SOR2_Register | Go | |
0x469 | Register_0x469_Register | Go | |
0x4A0 | RXFCFG_Register | Go | |
0x4A1 | RXFS_Register | Go | |
0x4A2 | RXFPMD1_Register | Go | |
0x4A3 | RXFPMD2_Register | Go | |
0x4A4 | RXFPMD3_Register | Go | |
0x4CD | Register_0x4cd | Go | |
0x4CE | Register_0x4ce | Go | |
0x4CF | Register_0x4cf | Go | |
0x4D0 | EEECFG2_Register | Go | |
0x4D1 | EEECFG3_Register | Go | |
0x4D2 | Register_0x4d2 | Go | |
0x4D4 | Register_0x4d4 | Go | |
0x4D5 | DSP_100M_STEP_2_Register | Go | |
0x4D6 | DSP_100M_STEP_3_Register | Go | |
0x4D7 | DSP_100M_STEP_4_Register | Go | |
0x1000 | MMD3_PCS_CTRL_1_Register | Go | |
0x1001 | MMD3_PCS_STATUS_1 | Go | |
0x1014 | MMD3_EEE_CAPABILITY_Register | Go | |
0x1016 | MMD3_WAKE_ERR_CNT_Register | Go | |
0x203C | MMD7_EEE_ADVERTISEMENT_Register | Go | |
0x203D | MMD7_EEE_LP_ABILITY_Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 12 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
H | H | Set or cleared by hardware |
R | R | Read |
Write Type | ||
W | W | Write |
W, SC | W | Write |
W, STRAP | W | Write |
W, STRAP (A-MDIX) | W | Write |
W, STRAP (ANEG_Dis) | W | Write |
W, STRAP (ANGE_Dis ) | W | Write |
W, STRAP( Master/Slave) | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |