JAJSID0G
december 2019 – july 2023
DP83826E
,
DP83826I
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Mode Comparison Tables
6
Pin Configuration and Functions (ENHANCED Mode)
7
Pin Configuration and Functions (BASIC Mode)
8
Specifications
8.1
絶対最大定格
8.2
ESD 定格
8.3
推奨動作条件
8.4
熱に関する情報
8.5
電気的特性
8.6
タイミング要件
8.7
Timing Diagrams
8.8
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Auto-Negotiation (Speed/Duplex Selection)
9.3.2
Auto-MDIX Resolution
9.3.3
Energy Efficient Ethernet
9.3.3.1
EEE Overview
9.3.3.2
EEE Negotiation
9.3.4
EEE for Legacy MACs Not Supporting 802.3az
9.3.5
Wake-on-LAN Packet Detection
9.3.5.1
Magic Packet Structure
9.3.5.2
Magic Packet Example
9.3.5.3
Wake-on-LAN Configuration and Status
9.3.6
Low Power Modes
9.3.6.1
Active Sleep
9.3.6.2
IEEE Power-Down
9.3.6.3
Deep Power Down State
9.3.7
RMII Repeater Mode
9.3.8
Clock Output
9.3.9
Media Independent Interface (MII)
9.3.10
Reduced Media Independent Interface (RMII)
9.3.11
Serial Management Interface
9.3.11.1
Extended Register Space Access
9.3.11.2
Write Address Operation
9.3.11.3
Read Address Operation
9.3.11.4
Write (No Post Increment) Operation
9.3.11.5
Read (No Post Increment) Operation
9.3.11.6
Example Write Operation (No Post Increment)
9.3.12
100BASE-TX
9.3.12.1
100BASE-TX Transmitter
9.3.12.1.1
Code-Group Encoding and Injection
9.3.12.1.2
Scrambler
9.3.12.1.3
NRZ to NRZI Encoder
9.3.12.1.4
Binary to MLT-3 Converter
9.3.12.2
100BASE-TX Receiver
9.3.13
10BASE-Te
9.3.13.1
Squelch
9.3.13.2
Normal Link Pulse Detection and Generation
9.3.13.3
Jabber
9.3.13.4
Active Link Polarity Detection and Correction
9.3.14
Loopback Modes
9.3.14.1
Near-end Loopback
9.3.14.2
MII Loopback
9.3.14.3
PCS Loopback
9.3.14.4
Digital Loopback
9.3.14.5
Analog Loopback
9.3.14.6
Far-End (Reverse) Loopback
9.3.15
BIST Configurations
9.3.16
Cable Diagnostics
9.3.16.1
Time Domain Reflectometry (TDR)
9.3.16.2
Fast Link-Drop Functionality
9.3.17
LED and GPIO Configuration
9.4
Programming
9.4.1
Hardware Bootstraps Configuration
9.4.1.1
DP83826 Bootstrap Configurations (ENHANCED Mode)
9.4.1.1.1
Bootstraps for PHY Address
9.4.1.2
DP83826 Strap Configuration (BASIC Mode)
9.4.1.2.1
Bootstraps for PHY Address
9.5
Register Maps
9.5.1
DP83826 Registers
10
Application and Implementation
10.1
Application Information
10.2
Typical Applications
10.2.1
Twisted-Pair Interface (TPI) Network Circuit
10.2.2
Transformer Recommendations
10.2.3
Capacitive DC Blocking
10.2.4
Design Requirements
10.2.4.1
Clock Requirements
10.2.4.1.1
Oscillator
10.2.4.1.2
Crystal
10.2.5
Detailed Design Procedure
10.2.5.1
MII Layout Guidelines
10.2.5.2
RMII Layout Guidelines
10.2.5.3
MDI Layout Guidelines
10.2.6
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.1.1
Signal Traces
12.1.2
Return Path
12.1.3
Transformer Layout
12.1.4
Metal Pour
12.1.5
PCB Layer Stacking
12.1.5.1
Layout Example
13
Device and Documentation Support
13.1
Related Documentation
13.2
Receiving Notification of Documentation Updates
13.3
Support Resources
13.4
Trademarks
13.5
静電気放電に関する注意事項
13.6
用語集
14
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RHB|32
MPQF130D
サーマルパッド・メカニカル・データ
RHB|32
QFND257K
発注情報
jajsid0g_oa
jajsid0g_pm
13.6
用語集
テキサス・インスツルメンツ用語集
この用語集には、用語や略語の一覧および定義が記載されています。