The DP83826 is a single-port physical layer transceiver compliant to IEEE802.3 10BASE-Te and 100BASE-TX standards. The DP83826 is designed to meet stringent Industrial fieldbus applications' needs and offers very low latency, deterministic variation in latency (across reset, power cycle), fixed phase between XI and TX_CLK, low power, and configuration using hardware bootstraps to achieve fast link up. The device supports the standard MII and RMII (Master mode and Slave mode) for direct connection to the media access controller (MAC). Its dedicated CLKOUT pin can be used to clock other modules on the system. In addition, the PWRDN pin controls the DP83826 link up from power-on-reset (POR) and helps with design of asynchronous power-up of the DP83826 and host system-on-a-chip (SoC) or field-programmable-gate-array (FPGA) controller.

The device operates from a single 3.3-V power supply and has an integrated LDO to provide voltage rails needed for internal blocks. The device allows I/O voltage interfaces of 3.3 V or 1.8 V, which in turn enables the DP83826 to operate as a single-supply PHY. Automatic supply configuration within the DP83826 allows for any combination of VDDIO supply without the need for additional configuration settings.

The DP83826 uses mixed-signal processing to perform equalization, data recovery, and error correction to achieve robust operation over a CAT5e twisted-pair cable length greater than 150 meters.

DP83826 offers two modes selectable during the power-up sequence using hardware bootstraps.

• BASIC mode
• ENHANCED mode

BASIC mode provides all the features required for standard Ethernet applications, using a common pinout configuration used in many of today's applications. This makes it easy to evaluate and test the product on existing platforms. The integrated MAC and MDI terminations streamline the design of boards when using the DP83826. All the required clock outputs are generated from a single PLL with a 25-MHz external crystal or oscillator input.

ENHANCED mode includes all the modes of operation described in BASIC Mode, however, the change in pins enable additional features. This makes it easy to use the DP83826 in ENHANCED Mode for Ethernet fieldbus applications in addition to the standard Ethernet applications. The feature includes:

• Dedicated Reference Clock Output: CLKOUT (pin 31) can be used to synchronize the whole system resulting in lower latency (reduced FIFO on MAC). This clock is enabled at POR and remains available across the reset. It also reduces the need for a dedicated clock for other PHYs and the host SoC/FPGA on the board.
• Dedicated HW Strap to use Force Mode, MDI or MDIX for fast link-up from POR and Reset.
• IEEE Power Down Pin: PWRDN (pin 21) helps asynchronous power-up of the DP83826 and host SoC/FPGA control, and can still manage the DP83826 link-up through this dedicated pin.
• PHY address hardware bootstraps on non MAC interface pins to improve Signal Integrity on MII and RMII MAC interface pins.

For pin maps of both modes, refer to section Section 6and Section 7.

To configure the hardware bootstraps for both modes, refer to sections Section 9.4.1.1 and Section 9.4.1.2.