SLLSEJ7 February   2015 DP83848-HT

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical System Diagram
  5. 5 Revision History
  6. 6 Bare Die Information
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Timing Specifications
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 100BASE-TX Transmitter
        1. 8.3.1.1 Code-Group Encoding and Injection
        2. 8.3.1.2 Scrambler
        3. 8.3.1.3 NRZ to NRZI Encoder
        4. 8.3.1.4 Binary to MLT-3 Convertor
      2. 8.3.2 100BASE-TX Receiver
        1. 8.3.2.1  Analog Front End
        2. 8.3.2.2  Digital Signal Processor
          1. 8.3.2.2.1 Digital Adaptive Equalization and Gain Control
          2. 8.3.2.2.2 Base Line Wander Compensation
        3. 8.3.2.3  Signal Detect
        4. 8.3.2.4  MLT-3 to NRZI Decoder
        5. 8.3.2.5  NRZI to NRZ
        6. 8.3.2.6  Serial to Parallel
        7. 8.3.2.7  Descrambler
        8. 8.3.2.8  Code-Group Alignment
        9. 8.3.2.9  4B/5B Decoder
        10. 8.3.2.10 100BASE-TX Link Integrity Monitor
        11. 8.3.2.11 Bad SSD Detection
      3. 8.3.3 10BASE-T Transceiver Module
        1. 8.3.3.1  Operational Modes
          1. 8.3.3.1.1 Half Duplex Mode
          2. 8.3.3.1.2 Full Duplex Mode
        2. 8.3.3.2  Smart Squelch
        3. 8.3.3.3  Collision Detection and SQE
        4. 8.3.3.4  Carrier Sense
        5. 8.3.3.5  Normal Link Pulse Detection/Generation
        6. 8.3.3.6  Jabber Function
        7. 8.3.3.7  Automatic Link Polarity Detection and Correction
        8. 8.3.3.8  Transmit and Receive Filtering
        9. 8.3.3.9  Transmitter
        10. 8.3.3.10 Receiver
      4. 8.3.4 Reset Operation
        1. 8.3.4.1 Hardware Reset
        2. 8.3.4.2 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 MII Interface
        1. 8.4.1.1 Nibble-Wide MII Data Interface
        2. 8.4.1.2 Collision Detect
        3. 8.4.1.3 Carrier Sense
      2. 8.4.2 Reduced MII Interface
      3. 8.4.3 10 Mb Serial Network Interface (SNI)
      4. 8.4.4 802.3u MII Serial Management Interface
        1. 8.4.4.1 Serial Management Register Access
        2. 8.4.4.2 Serial Management Access Protocol
        3. 8.4.4.3 Serial Management Preamble Suppression
    5. 8.5 Programming
      1. 8.5.1 Auto-Negotiation
        1. 8.5.1.1 Auto-Negotiation Pin Control
        2. 8.5.1.2 Auto-Negotiation Register Control
        3. 8.5.1.3 Auto-Negotiation Parallel Detection
        4. 8.5.1.4 Auto-Negotiation Restart
        5. 8.5.1.5 Enabling Auto-Negotiation via Software
        6. 8.5.1.6 Auto-Negotiation Complete Time
      2. 8.5.2 Auto-MDIX
      3. 8.5.3 PHY Address
        1. 8.5.3.1 MII Isolate Mode
      4. 8.5.4 LED Interface
        1. 8.5.4.1 LEDs
        2. 8.5.4.2 LED Direct Control
      5. 8.5.5 Half Duplex vs Full Duplex
      6. 8.5.6 Internal Loopback
      7. 8.5.7 BIST
    6. 8.6 Register Maps
      1. 8.6.1 Register Block
      2. 8.6.2 Register Definition
        1. 8.6.2.1 Basic Mode Control Register (BMCR)
        2. 8.6.2.2 Basic Mode Status Register (BMSR)
        3. 8.6.2.3 PHY Identifier Register 1 (PHYIDR1)
        4. 8.6.2.4 PHY Identifier Register 2 (PHYIDR2)
        5. 8.6.2.5 Auto-Negotiation Advertisement Register (ANAR)
        6. 8.6.2.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
        7. 8.6.2.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
        8. 8.6.2.8 Auto-Negotiate Expansion Register (ANER)
        9. 8.6.2.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)
      3. 8.6.3 Extended Registers
        1. 8.6.3.1  PHY Status Register (PHYSTS)
        2. 8.6.3.2  MII Interrupt Control Register (MICR)
        3. 8.6.3.3  MII Interrupt Status and Miscellaneous Control Register (MISR)
        4. 8.6.3.4  False Carrier Sense Counter Register (FCSCR)
        5. 8.6.3.5  Receiver Error Counter Register (RECR)
        6. 8.6.3.6  100 Mb/s PCS Configuration and Status Register (PCSR)
        7. 8.6.3.7  RMII and Bypass Register (RBR)
        8. 8.6.3.8  LED Direct Control Register (LEDCR)
        9. 8.6.3.9  PHY Control Register (PHYCR)
        10. 8.6.3.10 10Base-T Status/Control Register (10BTSCR)
        11. 8.6.3.11 CD Test and BIST Extensions Register (CDCTRL1)
        12. 8.6.3.12 Energy Detect Control (EDCR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Clock Requirements
        2. 9.2.1.2 Magnetics
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 TPI Network Circuit
        2. 9.2.2.2 Clock In (X1) Requirements
          1. 9.2.2.2.1 Oscillator
          2. 9.2.2.2.2 Crystal
        3. 9.2.2.3 Power Feedback Circuit
        4. 9.2.2.4 Power Down and Interrupt
          1. 9.2.2.4.1 Power-Down Control Mode
          2. 9.2.2.4.2 Interrupt Mechanisms
        5. 9.2.2.5 Energy Detect Mode
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layer Stacking
    2. 11.2 Layout Example
    3. 11.3 ESD Protection
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage –0.5 4.2 V
VIN DC input voltage –0.5 VCC + 0.5 V
VOUT DC output voltage –0.5 VCC + 0.5 V
TJ Operating junction temperature –55 150 °C
Tstg Storage temperature –65 150 °C

7.2 ESD Ratings

VALUE UNIT
V(ESD) ESD rating
(RZAP = 1.5 kΩ,
CZAP = 100 pF)		 Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions(1)

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 3 3.6 V
TA Operating free-air temperature(2) –55 150 °C
PD Power dissipation 267 mW
(1) Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits.
(2) Provided that Thermal Pad is soldered down.

7.4 Thermal Information

THERMAL METRIC(1) DP83848 UNIT
PHP
48 PINS
RθJA Junction-to-ambient thermal resistance 35.74 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 21.8
RθJB Junction-to-board thermal resistance 19.5
ψJT Junction-to-top characterization parameter 1.2
ψJB Junction-to-board characterization parameter 19.4
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input High Voltage Nominal VCC 2 V
VIL Input Low Voltage 0.8 V
IIH Input High Current VIN = VCC 10 µA
IIL Input Low Current VIN = GND 10 µA
VOL Output Low Voltage IOL = 4 mA 0.4 V
VOH Output High Voltage IOH = –4 mA VCC – 0.5 V
IOZ TRI-STATE Leakage VOUT = VCC, VOUT = GND ±10 µA
VTPTD_100 100M Transmit Voltage 0.89 1 1.15 V
VTPTDsym 100M Transmit Voltage Symmetry ±2%
VTPTD_10 10M Transmit Voltage 2.17 2.5 2.8 V
CIN1 CMOS Input Capacitance 5 pF
COUT1 CMOS Output Capacitance 5 pF
SDTHon 100BASE-TX Signal detect turnon threshold 1000 mV diff pk-pk
SDTHoff 100BASE-TX Signal detect turnoff threshold 200 mV diff pk-pk
VTH1 10BASE-T Receive Threshold 585 mV
Idd100 100BASE-TX (Full Duplex) 81 mA
Idd10 10BASE-T (Full Duplex) 92 mA
Idd Power Down Mode 14 mA

7.6 AC Timing Specifications

Table 1. Power-Up Timing

PARAMETER NOTES MIN TYP MAX UNIT
T2.1.1 Post power-up stabilization time prior to MDC preamble for register accesses MDIO is pulled high for 32-bit serial management initialization 167 ms
X1 Clock must be stable for a minimum of 167 ms at power up.
T2.1.2 Hardware configuration latching time from power up Hardware Configuration Pins are described in the Pin Description section 167 ms
X1 Clock must be stable for a minimum of 167 ms at power up.
T2.1.3 Hardware configuration pins transition to output drivers 50 ns
pwr_up_timing.gifFigure 1. Power-Up Timing

Table 2. Reset Timing

PARAMETER NOTES(1) MIN TYP MAX UNIT
T2.2.1 Post RESET Stabilization time prior to MDC preamble for register accesses MDIO is pulled high for 32-bit serial management initialization 3 µs
T2.2.2 Hardware configuration latching time from the deassertion of RESET (either soft or hard) 3 µs
T2.2.3 Hardware configuration pins transition to output drivers 50 ns
T2.2.4 RESET pulse width X1 Clock must be stable for at minimum of 1 µs during RESET pulse low time 1 µs
(1) It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.
reset_timing.gifFigure 2. Reset Timing

Table 3. MII Serial Management Timing

PARAMETER NOTES MIN TYP MAX UNIT
T2.3.1 MDC to MDIO (output) delay time 0 30 ns
T2.3.2 MDIO (input) to MDC setup time 10 ns
T2.3.3 MDIO (input) to MDC hold time 10 ns
T2.3.4 MDC frequency 2.5 25 MHz
serial_mangmt_timing.gifFigure 3. MII Serial Management Timing

Table 4. 100 Mb/s MII Transmit Timing

PARAMETER NOTES MIN TYP MAX UNIT
T2.4.1 TX_CLK high/low time 100 Mb/s normal mode 16 20 24 ns
T2.4.2 TXD[3:0], TX_EN data setup to TX_CLK 100 Mb/s normal mode 9.70 ns
T2.4.3 TXD[3:0], TX_EN data hold from TX_CLK 100 Mb/s normal mode 0 ns
transmit_timing.gifFigure 4. 100 Mb/s MII Transmit Timing

Table 5. 100 Mb/s MII Receive Timing

PARAMETER NOTES MIN TYP MAX UNIT
T2.5.1 RX_CLK high/low time 100 Mb/s normal mode 13 20 24 ns
T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER delay 100 Mb/s normal mode 20 ns
receive_timing.gifFigure 5. 100 Mb/s MII Receive Timing

Table 6. 100BASE-TX Transmit Packet Latency Timing

PARAMETER NOTES(1) MIN TYP MAX UNIT
T2.6.1 TX_CLK to PMD output pair latency 100 Mb/s normal mode 6 bits
(1) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
transmit_pack_latcy_timing.gifFigure 6. 100BASE-TX Transmit Packet Latency Timing

Table 7. 100BASE-TX Transmit Packet Deassertion Timing

PARAMETER NOTES(1) MIN TYP MAX UNIT
T2.7.1 TX_CLK to PMD output pair deassertion 100 Mb/s normal mode 6 bits
transmit_pack_deasstn_timing.gifFigure 7. 100BASE-TX Transmit Packet Deassertion Timing

Table 8. 100BASE-TX Transmit Timing (tR/F & Jitter)

PARAMETER NOTES(1)(2) MIN TYP MAX UNIT
T2.8.1 100 Mb/s PMD output pair tR and tF 2.6 4 5.5 ns
100 Mb/s tR and tF mismatch 710 ps
T2.8.2(3) 100 Mb/s PMD output pair transmit jitter 1.4 ns
(1) Normal Mismatch is the difference between the maximum and minimum of all rise and fall times.
(2) Rise and fall times taken at 10% and 90% of the +1 or –1 amplitude.
(3) Specified from –40°C to 125°C.
TX_transmit_timing.gifFigure 8. 100BASE-TX Transmit Timing (tR/F and Jitter)

Table 9. 100BASE-TX Receive Packet Latency Timing

PARAMETER(1) NOTES(2)(3) MIN TYP MAX UNIT
T2.9.1 Carrier sense ON delay 100 Mb/s normal mode 20 bits
T2.9.2 Receive data latency 100 Mb/s normal mode 24 bits
(1) Carrier sense ON delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
(2) 1 bit time = 10 ns in 100 Mb/s mode.
(3) PMD input pair voltage amplitude is greater than the signal detect turn-on threshold value.
TX_rec_pack_latcy_timing.gifFigure 9. 100BASE-TX Receive Packet Latency Timing

Table 10. 100BASE-TX Receive Packet Deassertion Timing

PARAMETER NOTES(1)(2) MIN TYP MAX UNIT
T2.10.1 Carrier sense OFF delay 100 Mb/s normal mode 24 bits
(1) Carrier sense off delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of carrier sense.
(2) 1 bit time = 10 ns in 100 Mb/s mode
TX_rec_pack_deasstn_timing.gifFigure 10. 100BASE-TX Receive Packet Deassertion Timing

Table 11. 10 Mb/s MII Transmit Timing

PARAMETER NOTES(1) MIN TYP MAX UNIT
T2.11.1 TX_CLK high/low time 10 Mb/s MII mode 160 200 240 ns
T2.11.2 TXD[3:0], TX_EN data setup to TX_CLK fall 10 Mb/s MII mode 24.70 ns
T2.11.3 TXD[3:0], TX_EN data hold from TX_CLK rise 10 Mb/s MII mode 0 ns
(1) An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on the falling edge of TX_CLK.
MII_transmit_timing.gifFigure 11. 10 Mb/s MII Transmit Timing

Table 12. 10 Mb/s MII Receive Timing

PARAMETER NOTES(1) MIN TYP MAX UNIT
T2.12.1 RX_CLK high/low time 130 200 240 ns
T2.12.2 RX_CLK to RXD[3:0], RX_DV delay 10 Mb/s MII mode 100 ns
T2.12.3 RX_CLK rising edge delay from RXD[3:0], RX_DV valid 10 Mb/s MII mode 245 ns
(1) RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.
MII_receive_timing.gifFigure 12. 10 Mb/s MII Receive Timing

Table 13. 10 Mb/s Serial Mode Transmit Timing

PARAMETER NOTES MIN TYP MAX UNIT
T2.13.1 TX_CLK high time 10 Mb/s serial mode 25 ns
T2.13.2 TX_CLK low time 10 Mb/s serial mode 75 ns
T2.13.3 TXD_0, TX_EN data setup to TX_CLK rise 10 Mb/s serial mode 24.70 ns
T2.13.4 TXD_0, TX_EN data hold from TX_CLK rise 10 Mb/s serial mode 6 ns
serial_mode_trans_timing.gifFigure 13. 10 Mb/s Serial Mode Transmit Timing

Table 14. 10 Mb/s Serial Mode Receive Timing

PARAMETER NOTES(1) MIN TYP MAX UNIT
T2.14.1 RX_CLK high/low time 50 ns
T2.14.2 RX_CLK fall to RXD_0, RX_DV delay 10 Mb/s serial mode 0 ns
(1) RX_CLK may be held high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.
serial_mode_recv_timing.gifFigure 14. 10 Mb/s Serial Mode Receive Timing

Table 15. 10BASE-T Transmit Timing (Start of Packet)

PARAMETER NOTES MIN TYP MAX UNIT
T2.15.1 Transmit output delay from the falling edge of TX_CLK 10 Mb/s MII mode 3.5 bits
T2.15.2 Transmit output delay from the rising edge of TX_CLK 10 Mb/s Serial mode 3.5 bits
T_trans_timg_start_pk.gifFigure 15. 10BASE-T Transmit Timing (Start of Packet)

Table 16. 10BASE-T Transmit Timing (End of Packet)

PARAMETER NOTES MIN TYP MAX UNIT
T2.16.1 End of packet high time (with ‘0’ ending bit) 300 ns
T2.16.2 End of packet high time (with ‘1’ ending bit) 300 ns
T_trans_timg_end_pk.gifFigure 16. 10BASE-T Transmit Timing (End of Packet)

Table 17. 10BASE-T Receive Timing (Start of Packet)

PARAMETER NOTES(1)(2) MIN TYP MAX UNIT
T2.17.1 Carrier sense turn on delay (PMD input pair to CRS) 630 1000 ns
T2.17.2 RX_DV latency 10 bits
T2.17.3 Receive data latency Measurement shown from SFD 8 bits
(1) 10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV
(2) 1 bit time = 100 ns in 10 Mb/s mode.
T_rec_timg_start_pk.gifFigure 17. 10BASE-T Receive Timing (Start of Packet)

Table 18. 10BASE-T Receive Timing (End of Packet)

PARAMETER NOTES MIN TYP MAX UNIT
T2.18.1 Carrier sense turn off delay 1 µs
T_rec_timg_end_pk.gifFigure 18. 10BASE-T Receive Timing (End of Packet)

Table 19. 10 Mb/s Heartbeat Timing

PARAMETER NOTES MIN TYP MAX UNIT
T2.19.1 CD heartbeat delay All 10 Mb/s modes 1200 ns
T2.19.2 CD heartbeat duration All 10 Mb/s modes 1000 ns
heartbeat_timing.gifFigure 19. 10 Mb/s Heartbeat Timing

Table 20. 10 Mb/s Jabber Timing

PARAMETER NOTES MIN TYP MAX UNIT
T2.20.1 Jabber activation time 85 ms
T2.20.2 Jabber deactivation time 500 ms
jabber_timing.gifFigure 20. 10 Mb/s Jabber Timing

Table 21. 10BASE-T Normal Link Pulse Timing

PARAMETER NOTES(1) MIN TYP MAX UNIT
T2.21.1 Pulse width 100 ns
T2.21.2 Pulse period 16 ms
(1) These specifications represent transmit timings.
T_normal_link_pulse_t.gifFigure 21. 10BASE-T Normal Link Pulse Timing

Table 22. Auto-Negotiation Fast Link Pulse (FLP) Timing

PARAMETER NOTES MIN TYP MAX UNIT
T2.22.1 Clock, data pulse width 100 ns
T2.22.2 Clock pulse to clock pulse period 125 μs
T2.22.3 Clock pulse to data pulse period Data = 1 62 μs
T2.22.4 Burst width 2 ms
T2.22.5 FLP burst to FLP burst period 16 ms
auto_neg_FLP_timing.gifFigure 22. Auto-Negotiation Fast Link Pulse (FLP) Timing

Table 23. 100BASE-TX Signal Detect Timing

PARAMETER NOTES(1) MIN TYP MAX UNIT
T2.23.1 SD internal turn-on time 1 ms
T2.23.2 SD internal turn-off time 350 µs
(1) The signal amplitude on PMD Input Pair must be TP-PMD compliant.
signal_detect_timing.gifFigure 23. 100BASE-TX Signal Detect Timing

Table 24. 100 Mb/s Internal Loopback Timing

PARAMETER NOTES(1)(2) MIN TYP MAX UNIT
T2.24.1 TX_EN to RX_DV loopback 100 Mb/s internal loopback mode 240 ns
(1) Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” of up to 550 μs during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is based on device delays after the initial 550μs “dead-time”.
(2) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
100_internal_loopback_t.gifFigure 24. 100 Mb/s Internal Loopback Timing

Table 25. 10 Mb/s Internal Loopback Timing

PARAMETER NOTES(1) MIN TYP MAX UNIT
T2.25.1 TX_EN to RX_DV loopback 10 Mb/s internal loopback mode 2.4 µs
(1) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
10_internal_loopback_t.gifFigure 25. 10 Mb/s Internal Loopback Timing

Table 26. RMII Transmit Timing

PARAMETER NOTES MIN TYP MAX UNIT
T2.26.1 X1 clock period 50-MHz reference clock 20 ns
T2.26.2 TXD[1:0], TX_EN, data setup to X1 rising 3.70 ns
T2.26.3 TXD[1:0], TX_EN, data hold from X1 rising 1.70 ns
T2.26.4 X1 clock to PMD output pair latency From X1 rising edge to first bit of symbol 17 bits
RMII_transmit_timing.gifFigure 26. RMII Transmit Timing

Table 27. RMII Receive Timing

PARAMETER NOTES(1)(2)(3) MIN TYP MAX UNIT
T2.27.1 X1 clock period 50 MHz Reference Clock 20 ns
T2.27.2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from X1 rising 6 ns
T2.27.3 CRS ON delay From JK symbol on PMD receive pair to initial assertion of CRS_DV 18.5 bits
T2.27.4 CRS OFF delay From TR symbol on PMD receive pair to initial deassertion of CRS_DV 27 bits
T2.27.5 RXD[1:0] and RX_ER latency From symbol on receive pair. Elasticity buffer set to default value (01). 38 bits
(1) Per the RMII Specification, output delays assume a 25-pF load.
(2) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the why. CRS_DV may toggle synchronously at the end of the packet to indicate CRS deassertion.
(3) RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data.
RMII_receive_timing.gifFigure 27. RMII Receive Timing

Table 28. Isolation Timing

PARAMETER NOTES MIN TYP MAX UNIT
T2.28.1 From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal Mode 100 µs
T2.28.2 From deassertion of software or hardware reset to transition from isolate to normal mode 500 µs
isolation_timing.gifFigure 28. Isolation Timing

Table 29. 25 MHz_OUT Timing

PARAMETER NOTES(1) MIN TYP MAX UNIT
T2.29.1 25 MHz_OUT high/low time MII mode 20 ns
RMII mode 10
T2.29.2 25 MHz_OUT propagation delay Relative to X1 8 ns
(1) 25 MHz_OUT characteristics are dependent upon the X1 input characteristics.
25MHz_out_timing.gifFigure 29. 25 MHz_OUT Timing

7.7 Typical Characteristics

op_life_2_llsec6.gif
  1. See data sheet for absolute maximum and minimum recommended operating conditions.
  2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).
  3. Enhanced plastic product disclaimer applies.
Figure 30. DP83848-HIREL Operating Life Derating Chart