SNOSAX1F May   2008  – September 2015 DP83849I

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 System Diagram
  2. 2 Revision History
  3. 3 Terminal Configuration and Functions
    1. 3.1 Pin Assignments
    2. 3.2 Signal Descriptions
      1. 3.2.1  Serial Management Interface
      2. 3.2.2  Clock Interface
      3. 3.2.3  MAC Data Interface
      4. 3.2.4  LED Interface
      5. 3.2.5  JTAG Interface
      6. 3.2.6  Reset and Power Down
      7. 3.2.7  Strap Options
      8. 3.2.8  PMD Interface for 10 Mb/s and 100 Mb/s
      9. 3.2.9  Special Connections
      10. 3.2.10 Power Supply Pins
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 DC Specifications
    6. 4.6 AC Timing Requirements
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Auto-Negotiation
        1. 5.3.1.1 Auto-Negotiation Pin Control
        2. 5.3.1.2 Auto-Negotiation Register Control
        3. 5.3.1.3 Auto-Negotiation Parallel Detection
        4. 5.3.1.4 Auto-Negotiation Restart
        5. 5.3.1.5 Auto-Negotiation Complete Time
        6. 5.3.1.6 Enabling Auto-Negotiation Through Software
      2. 5.3.2 Auto-MDIX
      3. 5.3.3 LED Interface
        1. 5.3.3.1 LEDs
        2. 5.3.3.2 LED Direct Control
      4. 5.3.4 Internal Loopback
      5. 5.3.5 BIST
      6. 5.3.6 Energy Detect Mode
      7. 5.3.7 Link Diagnostic Capabilities
        1. 5.3.7.1 Linked Cable Status
        2. 5.3.7.2 Polarity Reversal
          1. 5.3.7.2.1 Cable Swap Indication
          2. 5.3.7.2.2 100 MB Cable Length Estimation
          3. 5.3.7.2.3 Frequency Offset Relative to Link Partner
          4. 5.3.7.2.4 Cable Signal Quality Estimation
          5. 5.3.7.2.5 Link Quality Monitor
        3. 5.3.7.3 Link Quality Monitor Control and Status
          1. 5.3.7.3.1 Checking Current Parameter Values
          2. 5.3.7.3.2 Threshold Control
        4. 5.3.7.4 TDR Cable Diagnostics
          1. 5.3.7.4.1 TDR Pulse Generator
          2. 5.3.7.4.2 TDR Pulse Monitor
          3. 5.3.7.4.3 TDR Control Interface
          4. 5.3.7.4.4 TDR Results
    4. 5.4 Device Functional Modes
      1. 5.4.1 MII Interface
        1. 5.4.1.1 Nibble-wide MII Data Interface
        2. 5.4.1.2 Collision Detect
        3. 5.4.1.3 Carrier Sense
      2. 5.4.2 Reduced MII Interface
      3. 5.4.3 802.3u MII Serial Management Interface
        1. 5.4.3.1 Serial Management Register Access
        2. 5.4.3.2 Serial Management Preamble Suppression
        3. 5.4.3.3 Simultaneous Register Write
      4. 5.4.4 MAC Interface
        1. 5.4.4.1 10-Mb Serial Network Interface (SNI)
        2. 5.4.4.2 Single Clock MII Mode
        3. 5.4.4.3 Flexible MII Port Assignment
          1. 5.4.4.3.1 RX MII Port Mapping
          2. 5.4.4.3.2 TX MII Port Mapping
          3. 5.4.4.3.3 Common Flexible MII Port Configurations
        4. 5.4.4.4 Strapped Extender Mode
        5. 5.4.4.5 Notes and Restrictions
      5. 5.4.5 PHY Address
        1. 5.4.5.1 MII Isolate Mode
      6. 5.4.6 Half Duplex vs Full Duplex
      7. 5.4.7 Reset Operation
        1. 5.4.7.1 Hardware Reset
        2. 5.4.7.2 Full Software Reset
        3. 5.4.7.3 Soft Reset
    5. 5.5 Programming
      1. 5.5.1 Architecture
        1. 5.5.1.1 100BASE-TX Transmitter
          1. 5.5.1.1.1 Code-group Encoding and Injection
          2. 5.5.1.1.2 Scrambler
          3. 5.5.1.1.3 NRZ to NRZI Encoder
          4. 5.5.1.1.4 Binary to MLT-3 Convertor
      2. 5.5.2 100BASE-TX Receiver
      3. 5.5.3 Analog Front End
        1. 5.5.3.1  Digital Signal Processor
        2. 5.5.3.2  Digital Adaptive Equalization and Gain Control
        3. 5.5.3.3  Signal Detect
        4. 5.5.3.4  MLT-3 to NRZI Decoder
        5. 5.5.3.5  NRZI to NRZ
        6. 5.5.3.6  Serial to Parallel
        7. 5.5.3.7  Descrambler
        8. 5.5.3.8  Code-Group Alignment
        9. 5.5.3.9  4B/5B Decoder
        10. 5.5.3.10 100BASE-TX Link Integrity Monitor
        11. 5.5.3.11 BAD SSD Detection
      4. 5.5.4 10BASE-T Transceiver Module
        1. 5.5.4.1  Operational Modes
        2. 5.5.4.2  Smart Squelch
        3. 5.5.4.3  Collision Detection and SQE
        4. 5.5.4.4  Carrier Sense
        5. 5.5.4.5  Normal Link Pulse Detection/Generation
        6. 5.5.4.6  Jabber Function
        7. 5.5.4.7  Automatic Link Polarity Detection and Correction
        8. 5.5.4.8  Transmit and Receive Filtering
        9. 5.5.4.9  Transmitter
        10. 5.5.4.10 Receiver
    6. 5.6 Register Block
      1. 5.6.1 Register Definition
        1. 5.6.1.1  Basic Mode Control Register (BMCR)
        2. 5.6.1.2  Basic Mode Status Register (BMSR)
        3. 5.6.1.3  PHY Identifier Register #1 (PHYIDR1)
        4. 5.6.1.4  PHY Identifier Register #2 (PHYIDR2)
        5. 5.6.1.5  Auto-Negotiation Advertisement Register (ANAR)
        6. 5.6.1.6  Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
        7. 5.6.1.7  Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
        8. 5.6.1.8  Auto-Negotiate Expansion Register (ANER)
        9. 5.6.1.9  Auto-Negotiation Next Page Transmit Register (ANNPTR)
        10. 5.6.1.10 PHY Status Register (PHYSTS)
        11. 5.6.1.11 MII Interrupt Control Register (MICR)
        12. 5.6.1.12 MII Interrupt Status and Miscellaneous Control Register (MICR)
        13. 5.6.1.13 Page Select Register (PAGESEL)
      2. 5.6.2 Extended Registers - Page 0
        1. 5.6.2.1  False Carrier Sense Counter Register (FCSCR)
        2. 5.6.2.2  Receiver Error Counter Register (RECR)
        3. 5.6.2.3  100 Mb/s PCS Configuration and Status Register (PCSR)
        4. 5.6.2.4  RMII and Bypass Register (RBR)
        5. 5.6.2.5  LED Direct Control Register (LEDCR)
        6. 5.6.2.6  PHY Control Register (PHYCR)
        7. 5.6.2.7  10BASE-T Status/Control Register (10BTSCR)
        8. 5.6.2.8  CD Test and BIST Extensions Register (CDCTRL1)
        9. 5.6.2.9  Phy Control Register 2 (PHYCR2)
        10. 5.6.2.10 Energy Detect Control (EDCR)
      3. 5.6.3 Link Diagnostics Registers - Page 2
        1. 5.6.3.1  100Mb Length Detect Register (LEN100_DET), Page 2, address 14h
        2. 5.6.3.2  100Mb Frequency Offset Indication Register (FREQ100), Page 2, address 15h
        3. 5.6.3.3  TDR Control Register (TDR_CTRL), Page 2, address 16h
        4. 5.6.3.4  TDR Window Register (TDR_WIN), Page 2, address 17h
        5. 5.6.3.5  TDR Peak Register (TDR_PEAK), Page 2, address 18h
        6. 5.6.3.6  TDR Threshold Register (TDR_THR), Page 2, address 19h
        7. 5.6.3.7  Variance Control Register (VAR_CTRL), Page 2, address 1Ah
        8. 5.6.3.8  Variance Data Register (VAR_DATA), Page 2, address 1Bh
        9. 5.6.3.9  Link Quality Monitor Register (LQMR), Page 2, address 1Dh
        10. 5.6.3.10 Link Quality Data Register (LQDR), Page 2
  6. 6 Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 TPI Network Circuit
        2. 6.2.2.2 Clock In (X1) Requirements
          1. 6.2.2.2.1 Oscillator
          2. 6.2.2.2.2 Crystal
      3. 6.2.3 Power Feedback Circuit
      4. 6.2.4 Power Down/Interrupt
        1. 6.2.4.1 Power Down Control Mode
        2. 6.2.4.2 Interrupt Mechanisms
      5. 6.2.5 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 PCB Layer Stacking
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Community Resources
      1. 9.1.1 Community Resources
    2. 9.2 Trademarks
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Glossary
  10. 10Mechanical Packaging and Orderable Information
    1. 10.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Power Supply Recommendations

The device VDD supply pins must be bypassed with low-impedance 0.1-μF surface mount capacitors. To reduce EMI, the capacitors must be places as close as possible to the component VDD supply pins, preferably between the supply pins and the vias connecting to the power plane. In some systems it may be desirable to add 0-Ω resistors in series with supply pins, as the resistor pads provide flexibility if adding EMI beads becomes necessary to meet system level certification testing requirements. (See Figure 7-1) It is recommended the PCB have at least one solid ground plane and one solid VDD plane to provide a low impedance power source to the component. This also provides a low impedance return path for non-differential digital MII and clock signals. A 10.0-μF capacitor must also be placed near the PHY component for local bulk bypassing between the VDD and ground planes.

DP83849I vdd_bypass_layout_snls250.gif Figure 7-1 VDD Bypass Layout