JAJSR96A September 2023 – April 2024 DP83TC811-Q1
PRODUCTION DATA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Reserved | |||||||
RW-0000 0100 000 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
xMII Impedance Control | Reserved | ||||||
RW-1 000 | RW-0 |
BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
---|---|---|---|---|
15:5 | Reserved | RW | 0000 0100 000 | Reserved |
4:1 | xMII Impedance Control | RW | 1 000 | MAC Impedance Control: MAC Impedance Control sets the series termination value within the DP83TC811-Q1. This field controls the following pins: RX_D[3:0], RX_CLK, RX_ER, and RX_DV. 0 000 = 99Ω 0 001 = 91Ω 0 010 = 84Ω 0 011 = 78Ω 0 100 = 73Ω 0 101 = 69Ω 0 110 = 65Ω 0 111 = 61Ω 1 000 = 58Ω (default) 1 001 = 55Ω 1 010 = 53Ω 1 011 = 50Ω 1 100 = 48Ω 1 101 = 46Ω 1 110 = 44Ω 1 111 = 42Ω Note: Individual pin control is not supported. |
0 | Reserved | RW | 0 | Reserved |