JAJSJF5B April   2021  – January 2023 DP83TC812R-Q1 , DP83TC812S-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Diagnostic Tool Kit
        1. 8.3.1.1 Signal Quality Indicator
        2. 8.3.1.2 Electrostatic Discharge Sensing
        3. 8.3.1.3 Time Domain Reflectometry
        4. 8.3.1.4 Voltage Sensing
        5. 8.3.1.5 BIST and Loopback Modes
          1. 8.3.1.5.1 Data Generator and Checker
          2. 8.3.1.5.2 xMII Loopback
          3. 8.3.1.5.3 PCS Loopback
          4. 8.3.1.5.4 Digital Loopback
          5. 8.3.1.5.5 Analog Loopback
          6. 8.3.1.5.6 Reverse Loopback
      2. 8.3.2 Compliance Test Modes
        1. 8.3.2.1 Test Mode 1
        2. 8.3.2.2 Test Mode 2
        3. 8.3.2.3 Test Mode 4
        4. 8.3.2.4 Test Mode 5
    4. 8.4 Device Functional Modes
      1. 8.4.1  Power Down
      2. 8.4.2  Reset
      3. 8.4.3  Standby
      4. 8.4.4  Normal
      5. 8.4.5  Sleep Ack
      6. 8.4.6  Sleep Request
      7. 8.4.7  Sleep Fail
      8. 8.4.8  Sleep
      9. 8.4.9  Wake-Up
      10. 8.4.10 TC10 System Example
      11. 8.4.11 Media Dependent Interface
        1. 8.4.11.1 100BASE-T1 Master and 100BASE-T1 Slave Configuration
        2. 8.4.11.2 Auto-Polarity Detection and Correction
        3. 8.4.11.3 Jabber Detection
        4. 8.4.11.4 Interleave Detection
      12. 8.4.12 MAC Interfaces
        1. 8.4.12.1 Media Independent Interface
        2. 8.4.12.2 Reduced Media Independent Interface
        3. 8.4.12.3 Reduced Gigabit Media Independent Interface
        4. 8.4.12.4 Serial Gigabit Media Independent Interface
      13. 8.4.13 Serial Management Interface
      14. 8.4.14 Direct Register Access
      15. 8.4.15 Extended Register Space Access
      16. 8.4.16 Write Address Operation
        1. 8.4.16.1 MMD1 - Write Address Operation
      17. 8.4.17 Read Address Operation
        1. 8.4.17.1 MMD1 - Read Address Operation
      18. 8.4.18 Write Operation (No Post Increment)
        1. 8.4.18.1 MMD1 - Write Operation (No Post Increment)
      19. 8.4.19 Read Operation (No Post Increment)
        1. 8.4.19.1 MMD1 - Read Operation (No Post Increment)
      20. 8.4.20 Write Operation (Post Increment)
        1. 8.4.20.1 MMD1 - Write Operation (Post Increment)
      21. 8.4.21 Read Operation (Post Increment)
        1. 8.4.21.1 MMD1 - Read Operation (Post Increment)
    5. 8.5 Programming
      1. 8.5.1 Strap Configuration
      2. 8.5.2 LED Configuration
      3. 8.5.3 PHY Address Configuration
    6. 8.6 Register Maps
      1. 8.6.1 Register Access Summary
      2. 8.6.2 DP83TC812 Registers
  9. 9 Application and Implementation
    1. 9.1 アプリケーション情報に関する免責事項
    2. 9.2 Application Information
    3. 9.3 Typical Applications
      1. 9.3.1 Design Requirements
        1. 9.3.1.1 Physical Medium Attachment
          1. 9.3.1.1.1 Common-Mode Choke Recommendations
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Metal Pour
      4. 11.1.4 PCB Layer Stacking
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5.1 Strap Configuration

The DP83TC812S-Q1 uses functional pins as strap options to place the device into specific modes of operation. The values of these pins are sampled at power up and hardware reset (through either the RESET pin or register access). Some strap pins support 3 levels and some strap pins support 2 levels, which are described in greater detail below. PHY address straps, RX_DV/RX_CTRL and RX_ER, are 3-level straps while all other straps are two levels. Configuration of the device may be done through strapping or through serial management interface.

Note:

Because strap pins are functional pins after reset is deasserted, they must not be connected directly to VDDIO or VDDMAC or GND. Either pullup resistors, pulldown resistors, or both are required for proper operation.

Note:

When using VDDMAC and VDDIO separately, it is important to connect strap resistors to the correct voltage rail. Each pin's voltage domain is listed in the #GUID-72866B48-5936-4424-9F0F-D47E93DEC6DB/GUID-1661DC1A-7EDA-41E6-8C67-1F511F83A45A table below.

Figure 8-18 Strap Circuit

Rpulldn value is included in the Electrical Characteristics table of the data sheet.

Table 8-17 Recommended 3-Level Strap Resistor Ratios for PHY Address
MODE3 IDEAL RH (kΩ) (VDDIO = 3.3V)1 IDEAL RH (kΩ) (VDDIO = 2.5V)2 IDEAL RH (kΩ) (VDDIO = 1.8V)1
1 OPEN OPEN OPEN
2 13 12 4
3 4.5 2 0.8
  1. Strap resistors with 10% tolerance.
  2. Strap resistors with 1% tolerance.
  3. RL is optional and can be added if voltage on bootstrap pins needs to be adjusted.
Table 8-18 Recommended 2-Level Strap Resistors
MODE IDEAL RH (kΩ)1, 2
1 OPEN
2 2.49
  1. Strap resistors with up to 10% tolerance can be used.
  2. To gain more margin in customer application for 1.8V VDDIO, either 2.1 kΩ +/-10% pull-up can be used or resistor accuracy of 2.49 kΩ resistor can be limited to 1%.

The following table describes the PHY configuration bootstraps:

Table 8-19 Bootstraps
PIN
NAME		 PIN NO. DOMAIN DEFAULT
MODE		 STRAP FUNCTION DESCRIPTION
RX_DV/RX_CTRL 15 VDDMAC 1 MODE PHY_AD[0] PHY_AD[2] PHY_AD: PHY Address ID
1 0 0
2 0 1
3 1 1
RX_ER 14 VDDMAC 1 MODE PHY_AD[1] PHY_AD[3] PHY_AD: PHY Address ID
1 0 0
2 0 1
3 1 1
CLKOUT 16 VDDMAC 1 MODE AUTO AUTO: Autonomous Disable.
This is a duplicate strap for LED_1. If CLKOUT pin is configured as LED_1 pin then the AUTOstrap functionality also moves to the CLKOUT pin.
1 0
2 1
RX_D0 26 VDDMAC 1 MODE MAC[0] MAC: MAC Interface Selection
1 0
2 1
RX_D1 25 VDDMAC 1 MODE MAC[1] MAC: MAC Interface Selection
1 0
2 1
RX_D2 24 VDDMAC 1 MODE MAC[2] MAC: MAC Interface Selection
1 0
2 1
RX_D3 23 VDDMAC 1 MODE CLKOUT_PIN CLKOUT_PIN: This strap determines which pin will be used for output clock.
1 0
2 1
LED_0 35 VDDIO 1 MODE MS MS: 100BASE-T1 Master & 100BASE-T1 Slave Selection
1 0
2 1
LED_1 6 VDDIO 1 MODE AUTO AUTO: Autonomous Disable
This is the default strap pin for controlling AUTO feature. If this pin is configured as CLKOUT, the AUTO feature will move to pin 16.
1 0
2 1
Note: Refer to SNLA389 Application Note for more information about the register settings used for compliance testing. It is necessary to use these register settings to achieve the same performance as observed during compliance testing. Managed mode strap option is recommended to prevent the link up process from initiating while the software configuration from SNLA389 is being executed. Once the software configuration is completed, the PHY can be removed from Managed mode by setting bit 0x018B[6] to ‘1’. This bit is auto-cleared after link up

RX_D3 strap pin has a special functionality of controlling the output status of CLKOUT (pin 16) and LED_1 (pin 6). The #GUID-72866B48-5936-4424-9F0F-D47E93DEC6DB/GUID-4C4077AB-CCDC-4C3E-A825-A430D09414B7 table below shows how pin 16 and pin 6 will be affected by RX_D3 strap status. Note that RX_D3 option only changes the pin functionality but not their voltage domains. Pin 16 will always be in VDDMAC domain and Pin 6 will always be in VDDIO domain. If VDDIO and VDDMAC are at separate voltage levels, it must be ensured that pin 16 and pin 6 are strapped to their respective voltage domains.

In clock output daisy chain applications, if VDDMAC and VDDIO are at different voltages then clock output must be routed to pin 6. Internal oscillator of the DP83TC812 operates in the VDDIO domain, so clock ouput must also be used on the pin in VDDIO domain i.e. pin 6. In clock output daisy chain applications where VDDMAC and VDDIO are same, this requirement can be ignored. This requirement can also be ignored in applications where clock output is not being used.

Table 8-20 Clock Output Pin Selection
CLKOUT_PIN DESCRIPTION
0 Pin 16 is Clock output, Pin 6 is LED_1 pin. AUTO will be controlled by straps on pin 6.
1 Pin 6 is Clock output, Pin 16 is LED_1 pin. AUTO will be controlled by straps on pin 16.
Table 8-21 100BASE-T1 Master and 100BASE-T1 Slave Selection Bootstrap
MS DESCRIPTION
0 100BASE-T1 Slave Configuration
1 100BASE-T1 Master Configuration
Table 8-22 Autonomous Mode Bootstrap
AUTO DESCRIPTION
0 Autonomous Mode, PHY able to establish link after power-up
1 Managed Mode, PHY must be allowed to establish link after power-up based on register write
Table 8-23 MAC Interface Selection Bootstraps
MAC[2] MAC[1] MAC[0] DESCRIPTION
0 0 0 SGMII (4-wire)(1)
0 0 1 MII
0 1 0 RMII Slave
0 1 1 RMII Master
1 0 0 RGMII (Align Mode)
1 0 1 RGMII (TX Internal Delay Mode)
1 1 0 RGMII (TX and RX Internal Delay Mode)
1 1 1 RGMII (RX Internal Delay Mode)
(1) SGMII strap mode is only available on 'S' type device variant. For 'R' type device variant, this strap mode is RESERVED
Table 8-24 PHY Address Bootstraps
PHY_AD[3:0] RX_CTRL STRAP MODE RX_ER STRAP MODE DESCRIPTION #GUID-72866B48-5936-4424-9F0F-D47E93DEC6DB
0000 1 1 PHY Address: 0b00000 (0x0)
0001 - - NA
0010 - - NA
0011 - - NA
0100 2 1 PHY Address: 0b00100 (0x4)
0101 3 1 PHY Address: 0b00101 (0x5)
0110 - - NA
0111 - - NA
1000 1 2 PHY Address: 0b01000 (0x8)
1001 - - NA
1010 1 3 PHY Address: 0b01010 (0xA)
1011 - - NA
1100 2 2 PHY Address: 0b01010 (0xC)
1101 3 2 PHY Address: 0b01011 (0xD)
1110 2 3 PHY Address: 0b01110 (0xE)
1111 3 3 PHY Address: 0b01111 (0xF)