JAJSON9 May 2022 DP83TC813R-Q1 , DP83TC813S-Q1
PRODUCTION DATA
Table 8-25 lists the memory-mapped registers for the DP83TC813 registers. All register offset addresses not listed in Table 8-25 must be considered as reserved locations and the register contents must not be modified.
Complex bit access types are encoded to fit into small table cells. Table 8-26 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| H | H | Set or cleared by hardware |
| R | R | Read |
| RH | R H | Read Set or cleared by hardware |
| Write Type | ||
| W | W | Write |
| W0S | W 0S | Write 0 to set |
| W1S | W 1S | Write 1 to set |
| WSC | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
BMCR is shown in Figure 8-20 and described in Table 8-27.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| MII_reset | xMII Loopback | Manual_speed_MII | Auto-Negotiation Enable | Power Down | Isolate | RESERVED | Duplex Mode |
| RH/W1S-0b | R/W-0b | R-1b | R-0b | R/W-0b | R/W-0b | R-0b | R-1b |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | ||||||
| R/W-0b | R-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | MII_reset | RH/W1S | 0b | MII Reset. This bit will reset the Digital blocks of the PHY and return registers 0x0-0x0F back to default values. Other register will not be affected.
0b = No reset 1b = Digital in reset and all MII regs (0x0 - 0xF) reset to default |
| 14 | xMII Loopback | R/W | 0b | xMII Loopback:
1 = xMII Loopback enabled
0 = Normal Operation
When xMII loopback mode is activated, the transmitted data
presented on xMII TXD is looped back to xMII RXD internally.
There is no LINK indication generated when xMII loopback is
enabled.
1b = Enable Loopback from G/MII input to G/MII output |
| 13 | Manual_speed_MII | R | 1b | Speed Selection: Always 100-Mbps Speed |
| 12 | Auto-Negotiation Enable | R | 0b | Auto-Negotiation: Not supported on this device
0b = Disable Auto-Negotiation |
| 11 | Power Down | R/W | 0b | Power Down: The PHY is powered down after this bit is set. Only register access is enabled during this power down condition. The power down mode can be controlled via this bit or via INT_N pin. INT_N pin needs to be configured to operate as power down control. This bit is OR-ed with the input from the INT_N pin. When the active low INT_N is asserted, this bit is set. 0b = Normal Mode 1b = IEEE Power Down |
| 10 | Isolate | R/W | 0b | Isolate:Isolates the port from the xMII with the exception of the
serial management interface
0b = Normal Mode 1b = Enable Isolate Mode |
| 9 | RESERVED | R | 0b | Reserved |
| 8 | Duplex Mode | R | 1b | 1 = Full Duplex
0 = Half duplex
0b = Half duplex 1b = Full Duplex |
| 7 | RESERVED | R/W | 0b | Reserved |
| 6-0 | RESERVED | R | 0b | Reserved |
BMSR is shown in Figure 8-21 and described in Table 8-28.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| 100Base-T4 | 100Base-X Full Duplex | 100Base-X Half Duplex | 10 Mbps Full Duplex | 10 Mbps Half Duplex | RESERVED | ||
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MF Preamble Suppression | Auto-Negotiation Complete | Remote fault | Auto-Negotiation Ability | Link status | jabber detect | Extended Capability |
| R-0b | R-1b | R-1b | H-0b | R-0b | 0b | H-0b | R-1b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | 100Base-T4 | R | 0b | Always 0 - PHY not able to perform 100Base-T4 |
| 14 | 100Base-X Full Duplex | R | 0b | 1 = PHY able to perform full duplex 100Base-X
0 = PHY not able to perform full duplex 100Base-X
0b = PHY not able to perform full duplex 100Base-X 1b = PHY able to perform full duplex 100Base-X |
| 13 | 100Base-X Half Duplex | R | 0b | 1 = PHY able to perform half duplex 100Base-X
0 = PHY not able to perform half duplex 100Base-X
0b = PHY not able to perform half duplex 100Base-X 1b = PHY able to perform half duplex 100Base-X |
| 12 | 10 Mbps Full Duplex | R | 0b | 1 = PHY able to operate at 10Mbps in full duplex
0 = PHY not able to operate at 10Mbps in full duplex
0b = PHY not able to operate at 10Mbps in full duplex 1b = PHY able to operate at 10Mbps in full duplex |
| 11 | 10 Mbps Half Duplex | R | 0b | 1 = PHY able to operate at 10Mbps in half duplex
0 = PHY not able to operate at 10Mbps in half duplex
0b = PHY not able to operate at 10Mbps in half duplex 1b = PHY able to operate at 10Mbps in half duplex |
| 10-7 | RESERVED | R | 0b | Reserved |
| 6 | MF Preamble Suppression | R | 1b | 1 = PHY will accept management frames with preamble suppressed
0 = PHY will not accept management frames with preamble suppressed
0b = PHY will not accept management frames with preamble suppressed 1b = PHY will accept management frames with preamble suppressed |
| 5 | Auto-Negotiation Complete | R | 1b | 1 = Auto-Negotiation process completed
0 = Auto Negotiation process not completed (either still in process, disabled or reset)
0b = Auto Negotiation process not completed (either still in process, disabled or reset) 1b = Auto-Negotiation process completed |
| 4 | Remote fault | H | 0b | 1 = Remote fault condition detected
0 = No remote fault condition detected
0b = No remote fault condition detected 1b = Remote fault condition detected |
| 3 | Auto-Negotiation Ability | R | 0b | 1 = PHY is able to perform Auto-Negotiation
0 = PHY is not able to perform Auto-Negotiation
0b = PHY is not able to perform Auto-Negotiation 1b = PHY is able to perform Auto-Negotiation |
| 2 | Link status | 0b | Link Status bit
0b = Link is down 1b = Link is up | |
| 1 | jabber detect | H | 0b | 1= jabber condition detected
0 = No jabber condition detected
0b = No jabber condition detected 1b = jabber condition detected |
| 0 | Extended Capability | R | 1b | 1 = Extended register capabilities
0 = Basic register set capabilities only
0b = Basic register set capabilities only 1b = Extended register capabilities |
PHYIDR1 is shown in Figure 8-22 and described in Table 8-29.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Organizationally Unique Identifier Bits 21:6 | |||||||
| R-10000000000000b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Organizationally Unique Identifier Bits 21:6 | |||||||
| R-10000000000000b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | Organizationally Unique Identifier Bits 21:6 | R | 10000000000000b | Organizationally Unique Identification Number |
PHYIDR2 is shown in Figure 8-23 and described in Table 8-30.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Organizationally Unique Identifier Bits 5:0 | Model Number | ||||||
| R-101000b | R-100001b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Model Number | Revision Number | ||||||
| R-100001b | R-1b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | Organizationally Unique Identifier Bits 5:0 | R | 101000b | Organizationally Unique Identification Number |
| 9-4 | Model Number | R | 100001b | Vendor Model Number: The six bits of vendor model number are mapped from bits 9 to 4 |
| 3-0 | Revision Number | R | 1b | Device Revision Number
0b = Silicon Rev 1.0 1b = Silicon Rev 2.0 |
PHYSTS is shown in Figure 8-24 and described in Table 8-31.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | receive_error_latch | RESERVED | RESERVED | signal_detect | descrambler_lock | RESERVED |
| R-0b | R-0b | H-0b | H-0b | H-0b | R/W0S-0b | R/W0S-0b | R-0b |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| mii_interrupt | RESERVED | jabber_dtct | RESERVED | loopback_status | duplex_status | RESERVED | link_status |
| H-0b | R-0b | R-0b | H-0b | R-0b | R-1b | R-0b | R-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0b | Reserved |
| 14 | RESERVED | R | 0b | Reserved |
| 13 | receive_error_latch | H | 0b | RxerrCnt0 since last read.clear on read |
| 12 | RESERVED | H | 0b | Reserved |
| 11 | RESERVED | H | 0b | Reserved |
| 10 | signal_detect | R/W0S | 0b | Channel ok latch low
0b = Channel ok had been reset 1b = Channel ok is set |
| 9 | descrambler_lock | R/W0S | 0b | Descrambler lock latch low
0b = Descrmabler had been locked 1b = Descrambler is locked |
| 8 | RESERVED | R | 0b | Reserved |
| 7 | mii_interrupt | H | 0b | Interrupts pin status, cleared on reading 0x12 1b0 = Interrupts pin not set 1b1 = Interrupt pin had been set |
| 6 | RESERVED | R | 0b | Reserved |
| 5 | jabber_dtct | R | 0b | duplicate from reg.0x1.1 |
| 4 | RESERVED | H | 0b | Reserved |
| 3 | loopback_status | R | 0b | MII loopback status
0b = No MII loopback 1b = MII loopback |
| 2 | duplex_status | R | 1b | Duplex mode status
0b = Half duplex 1b = Full duplex |
| 1 | RESERVED | R | 0b | Reserved |
| 0 | link_status | R | 0b | duplication of reg.0x1.2 - link_status_bit
0b = Link is down 1b = Link is up |
PHYSCR is shown in Figure 8-25 and described in Table 8-32.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| dis_clk_125 | pwr_save_mode_en | pwr_save_mode | sgmii_soft_reset | use_PHYAD0_as_Isolate | tx_fifo_depth | ||
| R/W-0b | R/W-0b | R/W-0b | R/WSC-0b | R/W-0b | R/W-1b | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | int_pol | force_interrupt | INTEN | INT_OE | ||
| R/W-0b | R-0b | R/W-1b | R/W-0b | R/W-1b | R/W-1b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | dis_clk_125 | R/W | 0b | 1 = Disable CLK125 (Sourced by the CLK125 port)
1b = Disable CLK125 (Sourced by the CLK125 port) |
| 14 | pwr_save_mode_en | R/W | 0b | Enable power save mode config from reg |
| 13-12 | pwr_save_mode | R/W | 0b | Power Save Mode
0b = Normal mode 1b = IEEE mode: power down all digital and analog blocks, if bit [11] set to zero, PLL is also powered down 10 = Reserved 11 = Reserved |
| 11 | sgmii_soft_reset | R/WSC | 0b | Reset SGMII |
| 10 | use_PHYAD0_as_Isolate | R/W | 0b | 1- when phy_addr == 0, isolate MAC Interface
0- do not Isolate for PHYAD == 0.
0b = do not Isolate for PHYAD is 0. 1b = when phy_addr is 0, isolate MAC Interface |
| 9-8 | tx_fifo_depth | R/W | 1b | RMII TX fifo depth
0b = 4 nibbles 1b = 5 nibbles 1010b = 6 nibbles 1011b = 8 nibbles |
| 7 | RESERVED | R/W | 0b | Reserved |
| 6-4 | RESERVED | R | 0b | Reserved |
| 3 | int_pol | R/W | 1b | Interrupt Polarity
0b = Steady state (normal operation) without an interrupt is logical 0; during interrupt, pin is logical 1 1b = Steady state (normal operation) without an interrupt is logical 1; during interrupt, pin is logical 0 |
| 2 | force_interrupt | R/W | 0b | Force interrupt pin
0b = Do not force interrupt pin 1b = Force interrupt pin |
| 1 | INTEN | R/W | 1b | Enable interrupts
0b = Disable interrupts 1b = Enable interrupts |
| 0 | INT_OE | R/W | 1b | Interrupt/Power down pin configuration
0b = PIN is a power down PIN (input) 1b = PIN is an interrupt pin (output) |
MISR1 is shown in Figure 8-26 and described in Table 8-33.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| link_qual_int | energy_det_int | link_int | wol_int | esd_int | ms_train_done_int | fhf_int | rhf_int |
| H-0b | H-0b | H-0b | H-0b | H-0b | H-0b | H-0b | H-0b |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| link_qual_int_en | energy_det_int_en | link_int_en | wol_int_en | esd_int_en | ms_train_done_int_en | fhf_int_en | rhf_int_en |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | link_qual_int | H | 0b | Link quality(Not good) interrupt
0b = Link qual is Good 1b = Link qual is Not Good when link is ON. |
| 14 | energy_det_int | H | 0b | This INT can be asserted upon Rising edge only of energy_det signal using reg0x101 bit [0] : cfg_energy_det_int_le_only.
status output of energy_det_hist signal on reg0x19 bit[10].
0b = No Change of energy detected 1b = Change of energy_detected (both rising and falling edges) |
| 13 | link_int | H | 0b | Link status change interrupt
0b = No change of link status interrupt pending. 1b = Change of link status interrupt is pending and is cleared by the current read. |
| 12 | wol_int | H | 0b | Interrupt bit indicating that WOL packet is received
0b = No WoL interrupt pending. 1b = WoL packet received interrupt is pending and is cleared by the current read. |
| 11 | esd_int | H | 0b | 1 = ESD detected interrupt is pending and is cleared by the current read. 0 = No ESD interrupt pending. |
| 10 | ms_train_done_int | H | 0b | 1 = M/S Link Training Completed interrupt is pending and is cleared by the current read. 0 = No M/S Link Training Completed interrupt pending. |
| 9 | fhf_int | H | 0b | 1 = False carrier counter half-full interrupt is pending and is cleared by the current read. 0 = No false carrier counter half-full interrupt pending. |
| 8 | rhf_int | H | 0b | 1 = Receive error counter half-full interrupt is pending and is cleared by the current read. 0 = No receive error carrier counter half-full interrupt pending. |
| 7 | link_qual_int_en | R/W | 0b | Enable Interrupt on Link Quality status. |
| 6 | energy_det_int_en | R/W | 0b | Enable Interrupt on change of Energy Detect histr. Status |
| 5 | link_int_en | R/W | 0b | Enable Interrupt on change of link status |
| 4 | wol_int_en | R/W | 0b | Enable Interrupt on WoL detection |
| 3 | esd_int_en | R/W | 0b | Enable Interrupt on ESD detect event |
| 2 | ms_train_done_int_en | R/W | 0b | Enable Interrupt on M/S Link Training Completed event |
| 1 | fhf_int_en | R/W | 0b | Enable Interrupt on False Carrier Counter Register half-full event |
| 0 | rhf_int_en | R/W | 0b | Enable Interrupt on Receive Error Counter Register half-full event |
MISR2 is shown in Figure 8-27 and described in Table 8-34.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| under_volt_int | over_volt_int | RESERVED | RESERVED | RESERVED | sleep_int | pol_int | jabber_int |
| H-0b | H-0b | H-0b | H-0b | H-0b | H-0b | H-0b | H-0b |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| under_volt_int_en | over_volt_int_en | page_rcvd_int_en | Fifo_int_en | RESERVED | sleep_int_en | pol_int_en | jabber_int_en |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | under_volt_int | H | 0b | 1 = Under Voltage has been detected
0 =Under Voltage has not been detected
0b = Under Voltage has not been detected 1b = Under Voltage has been detected |
| 14 | over_volt_int | H | 0b | 1 = Over Voltage has been detected
0 = Over Voltage has not been detected
0b = Over Voltage has not been detected 1b = Over Voltage has been detected |
| 13 | RESERVED | H | 0b | Reserved |
| 12 | RESERVED | H | 0b | Reserved |
| 11 | RESERVED | H | 0b | Reserved |
| 10 | sleep_int | H | 0b | 1 = Sleep mode has changed
0 = Sleep mode has not changed
0b = Sleep mode has not changed 1b = Sleep mode has changed |
| 9 | pol_int | H | 0b | The device has auto-polarity correction when operating in slave mode. This bit will reflect if polarity was automatically swapped or not.
0b = Data polarity has not changed 1b = Data polarity has changed |
| 8 | jabber_int | H | 0b | 1 = Jabber detected
0 = Jabber not detected
0b = Jabber not detected 1b = Jabber detected |
| 7 | under_volt_int_en | R/W | 0b | 0 = Disable interrupt
0b = Disable interrupt |
| 6 | over_volt_int_en | R/W | 0b | 0 = Disable interrupt
0b = Disable interrupt |
| 5 | page_rcvd_int_en | R/W | 0b | 1 = Enable interrupt
1b = Enable interrupt |
| 4 | Fifo_int_en | R/W | 0b | 1 = Enable interrupt
1b = Enable interrupt |
| 3 | RESERVED | R/W | 0b | Reserved |
| 2 | sleep_int_en | R/W | 0b | 1 = Enable interrupt
1b = Enable interrupt |
| 1 | pol_int_en | R/W | 0b | 1 = Enable interrupt
1b = Enable interrupt |
| 0 | jabber_int_en | R/W | 0b | 1 = Enable interrupt
1b = Enable interrupt |
RECR is shown in Figure 8-28 and described in Table 8-35.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| rx_err_cnt | |||||||
| 0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| rx_err_cnt | |||||||
| 0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | rx_err_cnt | 0b | RX_ER Counter: When a valid carrier is presented (only while RX_DV is set), and there is at least one occurrence of an invalid data symbol, this 16-bit counter increments for each receive error detected. The RX_ER counter does not count in xMII loopback mode. The counter stops when it reaches its maximum count (0xFFFF). When the counter exceeds half-full (0x7FFF), an interrupt is generated. This register is cleared on read. |
BISCR is shown in Figure 8-29 and described in Table 8-36.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | prbs_sync_loss | RESERVED | core_pwr_mode | ||||
| R-0b | H-0b | R-0b | R-1b | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | tx_mii_lpbk | loopback_mode | pcs_lpbck | RESERVED | |||
| R-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0b | Reserved |
| 10 | prbs_sync_loss | H | 0b | Prbs lock lost latch status
0b = Prbs lock never lost 1b = Prbs lock had been lost |
| 9 | RESERVED | R | 0b | Reserved |
| 8 | core_pwr_mode | R | 1b | 1b0 = Core is in power down or sleep mode
1b1 = Core is is normal power mode
0b = Core is in power down or sleep mode 1b = Core is is normal power mode |
| 7 | RESERVED | R | 0b | Reserved |
| 6 | tx_mii_lpbk | R/W | 0b | Transmit data control during xMII Loopback
0b = Suppress data during xMII loopback 1b = Transmit data on MDI during xMII loopback |
| 5-2 | loopback_mode | R/W | 0b | Loopback Modes (Bit [1:0] must be 0)
1b = Digital Loopback 10b = Analog Loopback 100b = Reverse Loopback 1000b = External Loopback |
| 1 | pcs_lpbck | R/W | 0b | PCS loopback after PAM3
0b = Disable PCS Loopback 1b = Enable PCS Loopback |
| 0 | RESERVED | R/W | 0b | Reserved |
MISR3 is shown in Figure 8-30 and described in Table 8-37.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| wup_psv_int | no_link_int | sleep_fail_int | POR_done_int | no_frame_int | wake_req_int | WUP_sleep_int | LPS_int |
| H-0b | H-0b | H-0b | H-0b | H-0b | H-0b | H-0b | H-0b |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| wup_psv_int_en | no_link_int_en | sleep_fail_int_en | POR_done_int_en | no_frame_int_en | wake_req_int_en | WUP_sleep_int_en | LPS_int_en |
| R/W-X | R/W-0b | R/W-1b | R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-1b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | wup_psv_int | H | 0b | 0b = WUP are not received 1b = WUP received from remote PHY when in passive link |
| 14 | no_link_int | H | 0b | 1= Link has not been observed within time programmed in 0x562 once training has started.
0= Link up is still in progress or Link has already formed
0b = Link up is still in progress or Link has already formed 1b = Link has not been observed within time programmed in 0x562 once training has started. |
| 13 | sleep_fail_int | H | 0b | 0b = Sleep negotiation not failed yet 1b = Sleep negotiation failed |
| 12 | POR_done_int | H | 0b | 0b = POR not completed yet 1b = POR completed (required for re-initialization of registers when we come out of sleep) |
| 11 | no_frame_int | H | 0b | 0b = Frame was detected 1b = No Frame detected for transmission or reception in given time |
| 10 | wake_req_int | H | 0b | 0b = Wake-up request not received 1b = Wake-up request command was received from remote PHY |
| 9 | WUP_sleep_int | H | 0b | 0b = WUP not received 1b = WUP received from remote PHY when in sleep |
| 8 | LPS_int | H | 0b | 0b = LPS symbols not detected 1b = LPS symbols detetced |
| 7 | wup_psv_int_en | R/W | X | 0b = Disable interrupt 1b = Enable interrupt |
| 6 | no_link_int_en | R/W | 0b | 0b = Disable interrupt 1b = Enable interrupt |
| 5 | sleep_fail_int_en | R/W | 1b | 0b = Disable interrupt 1b = Enable interrupt |
| 4 | POR_done_int_en | R/W | 0b | 0b = Disable interrupt 1b = Enable interrupt |
| 3 | no_frame_int_en | R/W | 0b | 0b = Disable interrupt 1b = Enable interrupt |
| 2 | wake_req_int_en | R/W | 1b | 0b = Disable interrupt 1b = Enable interrupt |
| 1 | WUP_sleep_int_en | R/W | 0b | 0b = Disable interrupt 1b = Enable interrupt |
| 0 | LPS_int_en | R/W | 1b | 0b = Disable interrupt 1b = Enable interrupt |
REG_19 is shown in Figure 8-31 and described in Table 8-38.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | RESERVED | RESERVED | dsp_energy_detect | RESERVED | ||
| R-0b | R-0b | R-0b | R-1b | R-0b | R-0b | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADDR | ||||||
| R-0b | R-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | RESERVED | R | 0b | Reserved |
| 13 | RESERVED | R | 0b | Reserved |
| 12 | RESERVED | R | 0b | Reserved |
| 11 | RESERVED | R | 1b | Reserved |
| 10 | dsp_energy_detect | R | 0b | DSP energy detected status |
| 9-5 | RESERVED | R | 0b | Reserved |
| 4-0 | PHY_ADDR | R | 0b | PHY address decode from straps |
TC10_ABORT_REG is shown in Figure 8-32 and described in Table 8-39.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_tc10_abort_gpio_en | cfg_sleep_abort | |||||
| R-0b | R/W-0b | R/W-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-2 | RESERVED | R | 0b | Reserved |
| 1 | cfg_tc10_abort_gpio_en | R/W | 0b | enables aborting TC10 via GPIO.
one of CLKOUT/LED_1 pins which is being used as an LED can be used to abort
0b = disable TC10 abort via GPIO 1b = enable TC10 abort via GPIO |
| 0 | cfg_sleep_abort | R/W | 0b | loc_sleep_abprt as defined by TC10 standard.
Aborts sleep negotiation while in SLEEP_ACK state
0b = allow TC10 sleep negotiation 1b = abort TC10 sleep negotiation |
CDCR is shown in Figure 8-33 and described in Table 8-40.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| tdr_start | cfg_tdr_auto_run | RESERVED | |||||
| RH/W1S-0b | R/W-0b | R-0b | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | tdr_done | tdr_fail | |||||
| R-0b | R-0b | R-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | tdr_start | RH/W1S | 0b | clr by tdr done
Start TDR manually
0b = No TDR 1b = TDR start |
| 14 | cfg_tdr_auto_run | R/W | 0b | Enable TDR auto run on link down
0b = TDR start manually 1b = TDR start automatically on link down |
| 13-2 | RESERVED | R | 0b | Reserved |
| 1 | tdr_done | R | 0b | TDR done status
0b = TDR still not done 1b = TDR done |
| 0 | tdr_fail | R | 0b | TDR fail status |
PHYRCR is shown in Figure 8-34 and described in Table 8-41.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Software Global Reset | Digital reset | RESERVED | RESERVED | ||||
| RH/W1S-0b | RH/W1S-0b | R/W-0b | R/W-0b | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Standby_mode | RESERVED | RESERVED | RESERVED | ||||
| R/W-0b | R/W-0b | R-0b | R/W-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | Software Global Reset | RH/W1S | 0b | Hardware Reset(Reset digital + register file)
0b = Normal Operation 1b = Reset PHY. This bit is self cleared and has the same effect as the RESET pin. |
| 14 | Digital reset | RH/W1S | 0b | Software Restart
0b = Normal Operation 1b = Restart PHY. This bit is self cleared and resets all PHY circuitry except registers. |
| 13 | RESERVED | R/W | 0b | Reserved |
| 12-8 | RESERVED | R/W | 0b | Reserved |
| 7 | Standby_mode | R/W | 0b | Standby Mode
0b = Normal operation 1b = Standby mode enabled |
| 6 | RESERVED | R/W | 0b | Reserved |
| 5 | RESERVED | R | 0b | Reserved |
| 4-0 | RESERVED | R/W | 0b | Reserved |
Register_41 is shown in Figure 8-35 and described in Table 8-42.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_ether_type_pattern | |||||||
| R/W-1000100011110111b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_ether_type_pattern | |||||||
| R/W-1000100011110111b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | cfg_ether_type_pattern | R/W | 1000100011110111b | Ethertype pattern to be detected when 0x40[0] is enabled |
Register_133 is shown in Figure 8-36 and described in Table 8-43.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | link_up_c_and_s | link_status_pc | link_status | RESERVED | |||
| R-0b | R-0b | R-0b | R-0b | R-0b | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | descr_sync | loc_rcvr_status | rem_rcvr_status |
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0b | Reserved |
| 14 | link_up_c_and_s | R | 0b | link up for C&S |
| 13 | link_status_pc | R | 0b | PHY control in SEND_DATA state |
| 12 | link_status | R | 0b | link status set by link monitor |
| 11-8 | RESERVED | R | 0b | Reserved |
| 7 | RESERVED | R | 0b | Reserved |
| 6 | RESERVED | R | 0b | Reserved |
| 5 | RESERVED | R | 0b | Reserved |
| 4 | RESERVED | R | 0b | Reserved |
| 3 | RESERVED | R | 0b | Reserved |
| 2 | descr_sync | R | 0b | Status of descrambler
0b = Scrambler Not Locked 1b = Scrambler Locked |
| 1 | loc_rcvr_status | R | 0b | Local receiver status
0b = Local PHY received link invalid 1b = Local PHY received link valid |
| 0 | rem_rcvr_status | R | 0b | Remote receiver status
0b = Remote PHY received link invalid 1b = Remote PHY received link valid |
Register_17F is shown in Figure 8-37 and described in Table 8-44.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_en_wur_via_wake | cfg_en_wup_via_wake | RESERVED | |||||
| R/W-0b | R/W-1b | R-0b | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_wake_pin_len_fr_wur_th | |||||||
| R/W-101000b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | cfg_en_wur_via_wake | R/W | 0b | enable sending WUR when wake pin is asserted during active link.
Duration of pulse on WAKE pin can be configured in 0x17F[7:0]
0b = disable sending WUR when pulse on wake pin 1b = enable sending WUR when pulse on wake pin |
| 14 | cfg_en_wup_via_wake | R/W | 1b | enable sending WUP when device is woken by WAKE pin
0b = disables WUP 1b = enables WUP |
| 13-8 | RESERVED | R | 0b | Reserved |
| 7-0 | cfg_wake_pin_len_fr_wur_th | R/W | 101000b | Width of pulse in microseconds required to initiate WUR during an active link |
Register_180 is shown in Figure 8-38 and described in Table 8-45.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_sleep_req_timer_sel | RESERVED | cfg_sleep_ack_timer_sel | ||||
| R-0b | R/W-0b | R-0b | R/W-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-5 | RESERVED | R | 0b | Reserved |
| 4-3 | cfg_sleep_req_timer_sel | R/W | 0b | Configure sleep request timer
0b = 16ms 1b = 4ms 10b = 32ms 11b = 40ms |
| 2 | RESERVED | R | 0b | Reserved |
| 1-0 | cfg_sleep_ack_timer_sel | R/W | 0b | Configure sleep acknowledge timer
0b = 8ms 1b = 6ms 10b = 24ms 11b = 32ms |
Register_181 is shown in Figure 8-39 and described in Table 8-46.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | rx_lps_cnt | ||||||
| R-0b | R-0b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| rx_lps_cnt | |||||||
| R-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0b | Reserved |
| 9-0 | rx_lps_cnt | R | 0b | indicates number of LPS codes received |
Register_182 is shown in Figure 8-40 and described in Table 8-47.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | tx_lps_cnt | ||||||
| R-0b | R-0b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| tx_lps_cnt | |||||||
| R-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0b | Reserved |
| 9-0 | tx_lps_cnt | R | 0b | indicates number of WUR codes received |
LPS_CFG4 is shown in Figure 8-41 and described in Table 8-48.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_send_wup_dis_tx | cfg_force_lps_sleep_en | cfg_force_lps_sleep | cfg_force_tx_lps_en | cfg_force_tx_lps | cfg_force_lps_link_control_en | cfg_force_lps_link_control | cfg_force_lps_st_en |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_force_lps_st | ||||||
| R-0b | R/W-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | cfg_send_wup_dis_tx | R/W | 0b | Write 1 to this bit to send WUP when PHY control is in DISABLE_TRANSMIT state |
| 14 | cfg_force_lps_sleep_en | R/W | 0b | force control enable for sleep from LPS SM to PHY control SM |
| 13 | cfg_force_lps_sleep | R/W | 0b | force value for sleep from LPS SM to PHY control SM |
| 12 | cfg_force_tx_lps_en | R/W | 0b | force enable for TX_LPS |
| 11 | cfg_force_tx_lps | R/W | 0b | force value for TX_LPS |
| 10 | cfg_force_lps_link_control_en | R/W | 0b | force link control enable to LPS state machine |
| 9 | cfg_force_lps_link_control | R/W | 0b | force link control value from LPS state machine |
| 8 | cfg_force_lps_st_en | R/W | 0b | force enable for LPS state machine |
| 7 | RESERVED | R | 0b | Reserved |
| 6-0 | cfg_force_lps_st | R/W | 0b | force value of LPS state machine |
LPS_CFG is shown in Figure 8-42 and described in Table 8-49.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_reset_wur_cnt_rx_data | RESERVED | cfg_reset_lps_cnt_rx_data | RESERVED | cfg_reset_wur_cnt_tx_data | RESERVED | ||
| R/W-0b | R-0b | R/W-0b | R-0b | R/W-1b | R-0b | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_reset_lps_cnt_tx_data | cfg_wake_fwd_en_wup_psv_link | cfg_wake_fwd_man_trig | cfg_wake_fwd_dig_timer | cfg_wake_fwd_en_wur | cfg_wake_fwd_en_wup | |
| R-0b | R/W-0b | R/W-1b | R/W-0b | R/W-0b | R/W-1b | R/W-1b | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | cfg_reset_wur_cnt_rx_data | R/W | 0b | When set, resets the WUR received symbol counter upon receiving data |
| 14-13 | RESERVED | R | 0b | Reserved |
| 12 | cfg_reset_lps_cnt_rx_data | R/W | 0b | When set, resets the LPS received symbol counter upon receiving data |
| 11-10 | RESERVED | R | 0b | Reserved |
| 9 | cfg_reset_wur_cnt_tx_data | R/W | 1b | When set, resets the transmitted WUR symbols count when sending data |
| 8-7 | RESERVED | R | 0b | Reserved |
| 6 | cfg_reset_lps_cnt_tx_data | R/W | 0b | When set, resets the transmitted LPS symbols count when sending data |
| 5 | cfg_wake_fwd_en_wup_psv_link | R/W | 1b | control to enable/disable Wake forwarding on WAKE pin when WUP is received when in PASSIVE_LINK mode
0b = disables wake forwarding 1b = enables wake forwarding |
| 4 | cfg_wake_fwd_man_trig | R/W | 0b | Write 1 to manually generate Wake forwarding signal on WAKE pin. This bit is self-cleared |
| 3-2 | cfg_wake_fwd_dig_timer | R/W | 0b | when wake up request is received on an active link, the width of wake forwarding pulses are configurable to : 00: 50us 01: 500us 10: 2ms 11: 20ms |
| 1 | cfg_wake_fwd_en_wur | R/W | 1b | If set, enables doing wake forwarding when WUR symbols are received
0b = Don 't do wake forwarding on WAKE pin 1b = do wake forwarding on WAKE pin |
| 0 | cfg_wake_fwd_en_wup | R/W | 1b | If set, enables doing wake forwarding when WUP symbols are received
0b = Don 't do wake forwarding on WAKE pin 1b = do wake forwarding on WAKE pin |
LPS_CFG5 is shown in Figure 8-43 and described in Table 8-50.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_wup_timer | RESERVED | ||||||
| R/W-0b | R-0b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_rx_wur_sym_gap | cfg_rx_lps_sym_gap | |||||
| R-0b | R/W-0b | R/W-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | cfg_wup_timer | R/W | 0b | Time for which PHY control SM stays in WAKE_TRANSMIT b000: 1ms b001: 0.7ms b010: 1.3ms b011: 0.85ms b100: 1.5ms b101: 2ms b110: 2.5ms b111: 3ms |
| 12-4 | RESERVED | R | 0b | Reserved |
| 3-2 | cfg_rx_wur_sym_gap | R/W | 0b | max gap allowed b/w two WUR symbols for ack of WUR |
| 1-0 | cfg_rx_lps_sym_gap | R/W | 0b | max gap allowed b/w two LPS symbols for ack of LPS |
LPS_CFG7 is shown in Figure 8-44 and described in Table 8-51.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_tx_lps_stop_on_done | RESERVED | ||||||
| R/W-0b | R-0b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_tx_lps_sel | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | cfg_tx_lps_stop_on_done | R/W | 0b | configures the device to stop sending LPS codes once it is done sending the number of codes configures in 0x1879:0
0b = continues even after reaching limit 1b = stops after reaching limit |
| 14-8 | RESERVED | R | 0b | Reserved |
| 9-0 | cfg_tx_lps_sel | R/W | 0b | Indicates number of LPS symbols to be transmitted before tx_lps_done becomes true |
LPS_CFG8 is shown in Figure 8-45 and described in Table 8-52.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_tx_wur_sel | ||||||
| R-0b | R/W-10000000b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_tx_wur_sel | |||||||
| R/W-10000000b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0b | Reserved |
| 9-0 | cfg_tx_wur_sel | R/W | 10000000b | Indicates number of WUR symbols to be transmitted |
LPS_CFG9 is shown in Figure 8-46 and described in Table 8-53.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_rx_lps_sel | ||||||
| R-0b | R/W-1000000b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_rx_lps_sel | |||||||
| R/W-1000000b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0b | Reserved |
| 9-0 | cfg_rx_lps_sel | R/W | 1000000b | Indicates number of LPS symbols to be received to set lps_recv |
LPS_CFG10 is shown in Figure 8-47 and described in Table 8-54.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_rx_wur_sel | ||||||
| R-0b | R/W-1000000b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_rx_wur_sel | |||||||
| R/W-1000000b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0b | Reserved |
| 9-0 | cfg_rx_wur_sel | R/W | 1000000b | Indicates number of WUR symbols to be received to acknowlege WUR and do wake forwarding |
LPS_CFG3 is shown in Figure 8-48 and described in Table 8-55.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_lps_pwr_mode | ||||||
| R-0b | RH/W1S-0b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_lps_pwr_mode | |||||||
| RH/W1S-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-9 | RESERVED | R | 0b | Reserved |
| 8-0 | cfg_lps_pwr_mode | RH/W1S | 0b | 1b = Normal command 10b = Sleep request 10000b = Standby command 10000000b = WUR command 100000000b = Go to Passive Link command |
LPS_STATUS is shown in Figure 8-49 and described in Table 8-56.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | status_lps_st | ||||||
| R-0b | R-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-7 | RESERVED | R | 0b | Reserved |
| 6-0 | status_lps_st | R | 0b | LPS SM state
1b = SLEEP 10b = STANDBY 100b = NORMAL 1000b = SLEEP_ACK 10000b = SLEEP_REQ 100000b = SLEEP_FAIL 1000000b = SLEEP_SILENT 1000001b = PASSIVE_LINK |
TDR_TX_CFG is shown in Figure 8-50 and described in Table 8-57.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_tdr_tx_duration | |||||||
| R/W-10011100010000b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_tdr_tx_duration | |||||||
| R/W-10011100010000b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | cfg_tdr_tx_duration | R/W | 10011100010000b | TDR transmit duration in usec, Default : 10000usec |
TAP_PROCESS_CFG is shown in Figure 8-51 and described in Table 8-58.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_end_tap_index | ||||||
| R-0b | R/W-10111b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_start_tap_index | ||||||
| R-0b | R/W-11b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | RESERVED | R | 0b | Reserved |
| 12-8 | cfg_end_tap_index | R/W | 10111b | End echo coefficient index for peak detect sweep during TDR |
| 7-5 | RESERVED | R | 0b | Reserved |
| 4-0 | cfg_start_tap_index | R/W | 11b | Starting echo coefficient index for peak detect sweep during TDR |
TDR_CFG1 is shown in Figure 8-52 and described in Table 8-59.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_forward_shadow | cfg_post_silence_time | cfg_pre_silence_time | |||||
| R/W-100b | R/W-1b | R/W-1b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | RESERVED | R | 0b | Reserved |
| 7-4 | cfg_forward_shadow | R/W | 100b | Num of neighboring echo coeff taps to be considered for calculating local maximum |
| 3-2 | cfg_post_silence_time | R/W | 1b | Post-Silence state timer in ms 0x00 : 0ms 0x01 : 10ms 0x10 : 100ms 0x11 : 1000ms |
| 1-0 | cfg_pre_silence_time | R/W | 1b | Pre-Silence state timer in ms 0x00 : 0ms 0x01 : 10ms 0x10 : 100ms 0x11 : 1000ms |
TDR_CFG2 is shown in Figure 8-53 and described in Table 8-60.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_tdr_filt_loc_offset | ||||||
| R-0b | R/W-100b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_tdr_filt_init | |||||||
| R/W-11001b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | RESERVED | R | 0b | Reserved |
| 12-8 | cfg_tdr_filt_loc_offset | R/W | 100b | tap index offset of dyamic peak equation, cfg_start_tap_index + 1'b1 |
| 7-0 | cfg_tdr_filt_init | R/W | 11001b | Value of peak_th at x=start_tap_index of dynamic peak threshold equation |
TDR_CFG3 is shown in Figure 8-54 and described in Table 8-61.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_tdr_filt_slope | |||||||
| R/W-110000b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | RESERVED | R | 0b | Reserved |
| 7-0 | cfg_tdr_filt_slope | R/W | 110000b | Slope of dynamic peak threshold equation (0.4) |
TDR_CFG4 is shown in Figure 8-55 and described in Table 8-62.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | RESERVED | |||||
| R-0b | R/W-0b | R/W-0b | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | hpf_gain_tdr | pga_gain_tdr | ||||
| R/W-0b | R/W-0b | R/W-0b | R/W-100b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0b | Reserved |
| 9 | RESERVED | R/W | 0b | Reserved |
| 8-7 | RESERVED | R/W | 0b | Reserved |
| 6 | RESERVED | R/W | 0b | Reserved |
| 5-4 | hpf_gain_tdr | R/W | 0b | HPF gain code during TDR |
| 3-0 | pga_gain_tdr | R/W | 100b | PGA gain code during TDR |
TDR_CFG5 is shown in Figure 8-56 and described in Table 8-63.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_half_open_det_en | cfg_cable_delay_num | |||||
| R-0b | R/W-0b | R/W-1010b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-5 | RESERVED | R | 0b | Reserved |
| 4 | cfg_half_open_det_en | R/W | 0b | enables detection of half cable
0b = Disables half open detection 1b = Enbales half open detection |
| 3-0 | cfg_cable_delay_num | R/W | 1010b | Configure the propagation delay per meter of the cable in nanoseconds. This is used for the fault location estimation Valid values : 4 'd0 to 4 'd11 - [4.5:0.1:5.6]ns Default : 4 'd10 (5.5 ns) |
TDR_TC1 is shown in Figure 8-57 and described in Table 8-64.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | half_open_detect | ||||||
| R-0b | R-0b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| peak_detect | peak_sign | peak_loc_in_meters | |||||
| R-0b | R-0b | R-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-9 | RESERVED | R | 0b | Reserved |
| 8 | half_open_detect | R | 0b | Half wire open detect value
0b = Half wire open not detected 1b = Half wire open detected |
| 7 | peak_detect | R | 0b | Set if fault is detected in cable
0b = Fault not detected in cable 1b = Fault detected in cable |
| 6 | peak_sign | R | 0b | Nature of discontinuity. Valid only if peak_detect is set
0b = Short to GND, supply, or between MDI pins 1b = Open. Applicable to both 1-wire and 2-wire open faults |
| 5-0 | peak_loc_in_meters | R | 0b | Fault location in meters (Valid only if peak_detect is set) |
A2D_REG_48 is shown in Figure 8-58 and described in Table 8-65.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | dll_tx_delay_ctrl_rgmii_sl | |||||
| R-0b | R/W-0b | R/W-111b | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| dll_rx_delay_ctrl_rgmii_sl | RESERVED | ||||||
| R/W-111b | R/W-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | RESERVED | R | 0b | Reserved |
| 12 | RESERVED | R/W | 0b | Reserved |
| 11-8 | dll_tx_delay_ctrl_rgmii_sl | R/W | 111b | controls TX DLL in RGMII mode inSteps of 312.5ps, affects the CLK_90 output. Delay = ((Bit[11:8] in decimal) + 1)*312.5 ps |
| 7-4 | dll_rx_delay_ctrl_rgmii_sl | R/W | 111b | Controls RX DLL in RGMII mode in Steps of 312.5ps, affects the CLK_90 output. Delay = ((Bit[7:4] in decimal) + 1)*312.5 ps |
| 3-0 | RESERVED | R/W | 0b | Reserved |
LEDS_CFG_1 is shown in Figure 8-59 and described in Table 8-66.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | leds_bypass_stretching | leds_blink_rate | led_2_option | ||||
| R-0b | R/W-0b | R/W-10b | R/W-110b | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| led_1_option | led_0_option | ||||||
| R/W-1b | R/W-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0b | Reserved |
| 14 | leds_bypass_stretching | R/W | 0b | 0 - Noraml Operation
1 - Bypass LEDs stretching
0b = Noraml Operation 1b = Bypass LEDs stretching |
| 13-12 | leds_blink_rate | R/W | 10b | 0b = 20Hz (50mSec) 1b = 10Hz (100mSec) 1010b = 5Hz (200mSec) 1011b = 2Hz (500mSec) |
| 11-8 | led_2_option | R/W | 110b | Controlls LED_2 sources (same as bits 3:0) |
| 7-4 | led_1_option | R/W | 1b | Controlls LED_1 sources (same as bits 3:0) |
| 3-0 | led_0_option | R/W | 0b | Controlls LED_0 source:
0b = link OK 1b = link OK + blink on TX/RX activity 10b = link OK + blink on TX activity 11b = link OK + blink on RX activity 100b = link OK + 100Base-T1 Master 101b = link OK + 100Base-T1 Slave 110b = TX/RX activity with stretch option 111b = Reserved 1000b = Reserved 1001b = Link lost (remains on until register 0x1 is read) 1010b = PRBS error (toggles on error) 1011b = XMII TX/RX Error with stretch option |
LEDS_CFG_2 is shown in Figure 8-60 and described in Table 8-67.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| clk_o_gpio_ctrl_3 | led_1_gpio_ctrl_3 | led_0_gpio_ctrl_3 | RESERVED | led_2_drv_en | |||
| R/W-0b | R/W-0b | R/W-0b | R-0b | R/W-0b | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| led_2_drv_val | led_2_polarity | led_1_drv_en | led_1_drv_val | led_1_polarity | led_0_drv_en | led_0_drv_val | led_0_polarity |
| R/W-0b | R/W-1b | R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-0b | R/W-1b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | clk_o_gpio_ctrl_3 | R/W | 0b | MSB of CLKOUT gpio control. This bit provides additional options for configuring CLKOUT If set to 1, it changes the effect ofclk_o_gpio_ctrl bits of 0x453 Reg 0x453[2:0] will control CLKOUT as follows 0b = pwr_seq_done 1b = loc_wake_req from analog 10b = loc_wake_req to PHY control 11b = tx_lps_done 100b = tx_lps_done_64 101b = tx_lps 110b = pcs rx sm - receiving 111b = pcs tx sm - tx_enable |
| 14 | led_1_gpio_ctrl_3 | R/W | 0b | MSB of LED_1 gpio control. This bit provides additional options for configuring LED_0 If set to 1, it changes the effect of led_1_gpio_ctrl bits of 0x452 Reg 0x452[10:8] will control LED_1 as follows 0b = pwr_seq_done 1b = loc_wake_req from analog 10b = loc_wake_req to PHY control 11b = tx_lps_done 100b = tx_lps_done_64 101b = tx_lps 110b = pcs rx sm - receiving 111b = pcs tx sm - tx_enable |
| 13 | led_0_gpio_ctrl_3 | R/W | 0b | MSB of LED_0 gpio control. This bit provides additional options for configuring LED_0 If set to 1, it changes the effect of led_0_gpio_ctrl bits of 0x452 Reg 0x452[2:0] will control LED_0 as follows 0b = pwr_seq_done 1b = loc_wake_req from analog 10b = loc_wake_req to PHY control 11b = tx_lps_done 100b = tx_lps_done_64 101b = tx_lps 110b = pcs rx sm - receiving 111b = pcs tx sm - tx_enable |
| 12-9 | RESERVED | R | 0b | Reserved |
| 8 | led_2_drv_en | R/W | 0b | 0 - LED_2 is in normal operation mode
1 - Drive the value of LED_2 (driven value is bit 9)
0b = LED_2 is in normal operation mode 1b = Drive the value of LED_2 (driven value is bit 9) |
| 7 | led_2_drv_val | R/W | 0b | If bit #8 is set, this is the value of LED_2 |
| 6 | led_2_polarity | R/W | 1b | LED_2 polarity
0b = Active low 1b = Active high |
| 5 | led_1_drv_en | R/W | 0b | 0 - LED_1 is in normal operation mode
1 - Drive the value of LED_1 (driven value is bit #5)
0b = LED_1 is in normal operation mode 1b = Drive the value of LED_1 (driven value is bit #5) |
| 4 | led_1_drv_val | R/W | 0b | If bit #4 is set, this is the value of LED_1 |
| 3 | led_1_polarity | R/W | 1b | LED_1 polarity:
if(RX_D3_strap == 1)
reset_val = ~CLKOUT_strap
else
reset_val = ~LED_1_strap
0b = Active low 1b = Active high |
| 2 | led_0_drv_en | R/W | 0b | 0 - LED_0 is in normal operation mode 1 - Drive the value of LED_0 (driven value is bit #1) |
| 1 | led_0_drv_val | R/W | 0b | If bit #1 is set, this is the value of LED_1 |
| 0 | led_0_polarity | R/W | 1b | LED_0 polarity:
reset_val = ~LED_0_strap
0b = Active low 1b = Active high |
IO_MUX_CFG_1 is shown in Figure 8-61 and described in Table 8-68.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| led_1_clk_div_2_en | led_1_clk_source | led_1_clk_inv_en | led_1_gpio_ctrl | ||||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| led_0_clk_div_2_en | led_0_clk_source | led_0_clk_inv_en | led_0_gpio_ctrl | ||||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | led_1_clk_div_2_en | R/W | 0b | If led_1_gpio is configured to led_1_clk_source, Selects divide by 2 of clock at led_1_clk_source |
| 14-12 | led_1_clk_source | R/W | 0b | In case clk_out is MUXed to LED_1 IO, this field controls clk_out source: 000b - XI clock 001b - 200M pll clock 010b - 67 MHz ADC clock (recovered) 011b - Free 200MHz clock 100b - 25M MII clock derived from 200M LD clock 101b - 25MHz clock to PLL (XI or XI/2) or POR clock 110b - Core 100 MHz clock 111b - 67 MHz DSP clock (recovered, 1/3 duty cycle) |
| 11 | led_1_clk_inv_en | R/W | 0b | If led_1_gpio is configured to led_1_clk_source, Selects inversion of clock at led_1_clk_source |
| 10-8 | led_1_gpio_ctrl | R/W | 0b | controls the output of LED_1 IO: 000b - LED_1 (default: LINK + ACT) 001b - LED_1 Clock mux out 010b - WoL 011b - Under-Voltage indication 100b - 1588 TX 101b - 1588 RX 110b - ESD 111b - interrupt if(RX_D3_strap ==1) reset_val = 3'b001 else reset_val = 3'b000 |
| 7 | led_0_clk_div_2_en | R/W | 0b | If led_0_gpio is configured to led_0_clk_source, Selects divide by 2 of clock at led_0_clk_source |
| 6-4 | led_0_clk_source | R/W | 0b | In case clk_out is MUXed to LED_0 IO, this field controls clk_out source:
0b = XI clock 1b = 200M pll clock 10b = 67 MHz ADC clock (recovered) 11b = Free 200MHz clock 100b = 25M MII clock derived from 200M LD clock 101b = 25MHz clock to PLL (XI or XI/2) or POR clock 110b = Core 100 MHz clock 111b = 67 MHz DSP clock (recovered, 1/3 duty cycle) |
| 3 | led_0_clk_inv_en | R/W | 0b | If led_0_gpio is configured to led_0_clk_source, Selects inversion of clock at led_0_clk_source |
| 2-0 | led_0_gpio_ctrl | R/W | 0b | controls the output of LED_0 IO:
0b = LED_0 (default: LINK) 001b =LED_0 Clock mux out 010b = WoL 011b = Under-Voltage indication 100b = 1588 TX 101b = 1588 RX 110b = ESD 111b = interrupt |
IO_MUX_CFG_2 is shown in Figure 8-62 and described in Table 8-69.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_tx_er_on_led1 | RESERVED | clk_o_clk_div_2_en | |||||
| R/W-0b | R-0b | R/W-0b | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| clk_o_clk_source | clk_o_clk_inv_en | clk_o_gpio_ctrl | |||||
| R/W-0b | R/W-0b | R/W-1b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | cfg_tx_er_on_led1 | R/W | 0b | configures led_1 pin to tx_er pin and LED_1 pin is made input |
| 14-9 | RESERVED | R | 0b | Reserved |
| 8 | clk_o_clk_div_2_en | R/W | 0b | If clk_out is configured to output clk_o_clk_source, Selects divide by 2 of clock at clk_o_clk_source |
| 7-4 | clk_o_clk_source | R/W | 0b | In case clk_out is MUXed to CLK_O IO, this field controls clk_out source:
0000b - XI clock 0001b - 200M pll clock 0010b - 67 MHz ADC clock (recovered) 0011b - Free 200MHz clock 0100b - 25M MII clock derived from 200M LD clock 0101b - 25MHz clock to PLL (XI or XI/2) or POR clock 0110b - Core 100 MHz clock 0111b - 67 MHz DSP clock (recovered, 1/3 duty cycle) 1000b - CLK25_50 (50 MHz in RMII, 25 MHz in others) 1001b - 50M RMII RX clk 1010b - SGMII serlz clk 1011b - SGMII deserlz clk 1100b - 30ns tick 1101b - 40ns tick 1110b - DLL TX CLK 1111b - DLL RX CLK |
| 3 | clk_o_clk_inv_en | R/W | 0b | If clk_out is configured to output clk_o_clk_source, Selects inversion of clock at clk_o_clk_source |
| 2-0 | clk_o_gpio_ctrl | R/W | 1b | controls the output of CLK_O IO: 000b - LED_1 001b - CLKOUT Clock mux out 010b - WoL 011b - Under-Voltage indication 100b - 1588 TX 101b - 1588 RX 110b - ESD 111b - interrupt Automatically gets configured to 3 'h0 if pin6(LED_1) is strapped As daisy chain CLKOUT if(RX_D3_strap ==1) reset_val = 3'b000 else reset_val = 3'b001 |
IO_MUX_CFG is shown in Figure 8-63 and described in Table 8-70.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| rx_pins_pupd_value | rx_pins_pupd_force_control | tx_pins_pupd_value | tx_pins_pupd_force_control | mac_rx_impedance_ctrl | |||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| mac_rx_impedance_ctrl | mac_tx_impedance_ctrl | ||||||
| R/W-0b | R/W-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | rx_pins_pupd_value | R/W | 0b | when RX pins PUPD force control is enabled,
PUPD is contolled by this register
0b = No pull 1b = Pull up 10b = Pull down 11b = Reserved |
| 13 | rx_pins_pupd_force_control | R/W | 0b | enables PUPD force control on RX MAC pins
0b = No force control 1b = enables force control |
| 12-11 | tx_pins_pupd_value | R/W | 0b | when TX pins PUPD force control is enabled,
PUPD is contolled by this register
0b = No pull 1b = Pull up 10b = Pull down 11b = Reserved |
| 10 | tx_pins_pupd_force_control | R/W | 0b | enables PUPD force control on TX MAC pins
0b = No force control 1b = enables force control |
| 9-5 | mac_rx_impedance_ctrl | R/W | 0b | RX MAC interface PAD impedance control |
| 4-0 | mac_tx_impedance_ctrl | R/W | 0b | TX MAC interface PAD impedance control |
IO_STATUS_1 is shown in Figure 8-64 and described in Table 8-71.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| io_status_1 | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| io_status_1 | |||||||
| R-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | io_status_1 | R | 0b | If IO direction is controlled via register (IO_MUX_CFG) and (IO_INPUT_MODE_1), and direction is INPUT (i.e. io_oe_n_force_ctrl=1, io_input_mode[*]=1) - shows the current value of the following IOs: bit 0 - RX_D3 bit 1 - TX_CLK bit 2 - TX_EN bit 3 - TX_D0 bit 4 - TX_D1 bit 5 - TX_D2 bit 6 - TX_D3 bit 7 - INT_N bit 8 - CLKOUT bit 9 - LED_0 bit 10 - RX_CLK bit 11 - RX_DV bit 12 - 0 bit 13 - RX_ERR bit 14 - LED_1 bit 15 - RX_D0 |
IO_STATUS_2 is shown in Figure 8-65 and described in Table 8-72.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | io_status_2 | ||||||
| R-0b | R-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-2 | RESERVED | R | 0b | Reserved |
| 1-0 | io_status_2 | R | 0b | "If IO direction is controlled via register (IO_MUX_CFG) and (IO_INPUT_MODE_2), and direction is INPUT (i.e. io_oe_n_force_ctrl=1, io_input_mode[*]=1) - shows the current value of the following IOs: bit 0 - RX_D1 bit 1 - RX_D2 " |
CHIP_SOR_1 is shown in Figure 8-66 and described in Table 8-73.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | LED1_POR | RX_D3_POR | RESERVED | RESERVED | LED0_STRAP | RXD3_STRAP |
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RXD2_STRAP | RXD1_STRAP | RXD0_STRAP | RXCLK_STRAP | RXER_STRAP | RXDV_STRAP | ||
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0b | |
| 14 | RESERVED | R | 0b | Reserved |
| 13 | LED1_POR | R | 0b | LED_1 strap sampled at power up |
| 12 | RX_D3_POR | R | 0b | RX_D3 strap sampled at power up |
| 11 | RESERVED | R | 0b | Reserved |
| 10 | RESERVED | R | 0b | Reserved |
| 9 | LED0_STRAP | R | 0b | LED_0 strap sampled at power up or reset |
| 8 | RXD3_STRAP | R | 0b | RX_D3 strap sampled at reset |
| 7 | RXD2_STRAP | R | 0b | RX_D2 strap sampled at power up or reset |
| 6 | RXD1_STRAP | R | 0b | RX_D1 strap sampled at power up or reset |
| 5 | RXD0_STRAP | R | 0b | RX_D0 strap sampled at power up or reset |
| 4 | RXCLK_STRAP | R | 0b | RX_CLK strap sampled at power up or reset |
| 3-2 | RXER_STRAP | R | 0b | RX_ER strap sampled at power up or reset |
| 1-0 | RXDV_STRAP | R | 0b | RX_DV strap sampled at power up or reset |
LED1_CLKOUT_ANA_CTRL is shown in Figure 8-67 and described in Table 8-74.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | RESERVED | |||||
| R/W-0b | R/W-0b | R-0b | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | clkout_ana_sel_1p0v_sl | led_1_ana_mux_ctrl | clkout_ana_mux_ctrl | ||||
| R-0b | R/W-0b | R/W-11b | R/W-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R/W | 0b | Reserved |
| 14 | RESERVED | R/W | 0b | Reserved |
| 13-5 | RESERVED | R | 0b | Reserved |
| 4 | clkout_ana_sel_1p0v_sl | R/W | 0b | For selecting test line b/w analog test clocks |
| 3-2 | led_1_ana_mux_ctrl | R/W | 11b | Selects the signal to be sent out on LED_1 pin
Automatically selects
output from digital if
Pin6(LED_1) is strapped
As daisy chain CLKOUT
if(RX_D3_strap == 1)
reset_val = 2'b00
else
reset_val = 2'b11
0b = Daisy chain clock 1b = TX_TCLK for test modes 10b = ANA Test clock 11b = clkout_out_1p0v_sl from digital |
| 1-0 | clkout_ana_mux_ctrl | R/W | 0b | Selects the signal to be sent out on CLKOUT pin
Automatically selects
output from digital if
Pin6(LED_1) is strapped
As daisy chain CLKOUT
if(RX_D3_strap == 1)
reset_val = 2'b11
else
reset_val = 2'b00
0b = Daisy chain clock 1b = TX_TCLK for test modes 10b = ANA Test clock 11b = clkout_out_1p0v_sl from digital |
PCS_CTRL_1 is shown in Figure 8-68 and described in Table 8-75.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_force_slave_phase1_done | cfg_dis_ipg_scr_lock_check | cfg_link_control | RESERVED | cfg_desc_first_lock_count | ||
| R-0b | R/W-0b | R/W-0b | R/W-1b | R-0b | R/W-1111000b | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_desc_first_lock_count | |||||||
| R/W-1111000b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0b | Reserved |
| 14 | cfg_force_slave_phase1_done | R/W | 0b | Force to say phase1 of DSP slave training done |
| 13 | cfg_dis_ipg_scr_lock_check | R/W | 0b | Disable scrambler lock check during IPG |
| 12 | cfg_link_control | R/W | 1b | Enable for the entire training/linkup to start |
| 11-9 | RESERVED | R | 0b | Reserved |
| 8-0 | cfg_desc_first_lock_count | R/W | 1111000b | Number of idle symbols to decide on scrambler lock |
PCS_CTRL_2 is shown in Figure 8-69 and described in Table 8-76.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_desc_error_count | |||||||
| R/W-1010b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_rem_rcvr_sts_error_cnt | ||||||
| R-0b | R/W-101b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | cfg_desc_error_count | R/W | 1010b | Number of non-idle ymbols to look for to say scrambler unlocked |
| 7-5 | RESERVED | R | 0b | Reserved |
| 4-0 | cfg_rem_rcvr_sts_error_cnt | R/W | 101b | No of error symbols to rem rcvr status to go low |
TX_INTER_CFG is shown in Figure 8-70 and described in Table 8-77.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_force_tx_interleave | cfg_tx_interleave_en | cfg_interleave_det_en | ||||
| R-0b | R/W-0b | R/W-0b | R/W-1b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-3 | RESERVED | R | 0b | Reserved |
| 2 | cfg_force_tx_interleave | R/W | 0b | Force interleave on Tx |
| 1 | cfg_tx_interleave_en | R/W | 0b | Enable interleave on tx, if interleave detected on the Rx
0b = Interleave on Tx disabled 1b = Interleave on Tx enabled if interleave detected on Rx |
| 0 | cfg_interleave_det_en | R/W | 1b | Enable interleave detection
0b = Disable Interleave Detection 1b = Enable Interleave Detection |
JABBER_CFG is shown in Figure 8-71 and described in Table 8-78.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_rcv_jab_timer_val | ||||||
| R-0b | R/W-10001001100b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_rcv_jab_timer_val | |||||||
| R/W-10001001100b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0b | Reserved |
| 10-0 | cfg_rcv_jab_timer_val | R/W | 10001001100b | Jabber timeout count in usec |
TEST_MODE_CTRL is shown in Figure 8-72 and described in Table 8-79.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_test_mode1_symbol_cnt | ||||||
| R-0b | R/W-11100b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_test_mode1_symbol_cnt | RESERVED | ||||||
| R/W-11100b | R-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0b | Reserved |
| 9-4 | cfg_test_mode1_symbol_cnt | R/W | 11100b | number of +1/-1 symbols to send in test_mode_1 N= 2 + 2* CFG_TEST_MODE1_SYMBOL_CNT |
| 3-0 | RESERVED | R | 0b | Reserved |
RXF_CFG is shown in Figure 8-73 and described in Table 8-80.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| bits_nibbles_swap | sfd_byte | RESERVED | RESERVED | RESERVED | RESERVED | ||
| R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-0b | R/W-0b | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| enhanced_mac_support | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | bits_nibbles_swap | R/W | 0b | Option to swap bits / nibbles inside every RX data byte
0b = regular order, no swaps - RXD[3-0] 1b = swap bits order - RXD[0-3] 1010b = swap nibbles order - { RXD[3-0] , RXD[7-4] } 1011b = swap bits order in each nibble - { RXD[4-7] , RXD[0-3] } |
| 13 | sfd_byte | R/W | 0b | 0 - SFD is 0xD5 (i.e. RXF module searchs 0xD5)
1 - SFD is 0x5D (i.e. RXF module searchs 0x5D)
0b = SFD is 0xD5 (i.e. RXF module searchs 0xD5) 1b = SFD is 0x5D (i.e. RXF module searchs 0x5D) |
| 12 | RESERVED | R/W | 1b | Reserved |
| 11 | RESERVED | R/W | 0b | Reserved |
| 10-9 | RESERVED | R/W | 0b | Reserved |
| 8 | RESERVED | R/W | 0b | Reserved |
| 7 | enhanced_mac_support | R/W | 0b | Enables enhanced RX features. This bit shall be set when using wakeup abilities, CRC check or RX 1588 indication |
| 6 | RESERVED | R/W | 0b | Reserved |
| 5 | RESERVED | R/W | 0b | Reserved |
| 4 | RESERVED | R/W | 0b | Reserved |
| 3 | RESERVED | R/W | 0b | Reserved |
| 2 | RESERVED | R/W | 0b | Reserved |
| 1 | RESERVED | R | 0b | Reserved |
| 0 | RESERVED | R/W | 0b | Reserved |
PG_REG_4 is shown in Figure 8-74 and described in Table 8-81.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | force_pol_en | force_pol_val | RESERVED | ||||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | RESERVED | R/W | 0b | Reserved |
| 13 | force_pol_en | R/W | 0b | Enable force on polarity
0b = Auto-polarity on MDI 1b = Force polarity on MDI |
| 12 | force_pol_val | R/W | 0b | Polarity force value. Only valid if bit [13] is 1.
0b = Forced Normal polarity 1b = Forced Inverted polarity |
| 11-0 | RESERVED | R/W | 0b | Reserved |
TC1_CFG_RW is shown in Figure 8-75 and described in Table 8-82.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | cfg_link_status_metric | cfg_link_failure_multihot | ||||
| R-0b | R/W-0b | R/W-0b | R/W-111111b | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_link_failure_multihot | cfg_comm_timer_thrs | cfg_bad_sqi_thrs | |||||
| R/W-111111b | R/W-0b | R/W-100b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | RESERVED | R | 0b | Reserved |
| 13 | RESERVED | R/W | 0b | Reserved |
| 12-11 | cfg_link_status_metric | R/W | 0b | selects following link up signals as defined by C&S
0b = link_up_c_and_s 1b = link_montor_status 10b = (phy_control = SEND_DATA) 11b = comm_ready from TC1 spec |
| 10-5 | cfg_link_failure_multihot | R/W | 111111b | each bit enables logging of link failure in the given scenario: bit[5] - SQI greater than configured thershold in register cfg_bad_sqi_thrs bit[6] - RCV_JABBER_DET5 - BAD_SSD bit[7] - LINK_FAILED bit[8] - RX_ERROR bit[9] - BAD_END bit[10] - RESERVED |
| 4-3 | cfg_comm_timer_thrs | R/W | 0b | selects the hysteresis timer value for TC1 comm ready
0b = 2ms 1b = 500us 10b = 1ms 11b = 4ms |
| 2-0 | cfg_bad_sqi_thrs | R/W | 100b | SQI threshold used to increment Link Failure Count defined by TC1. Whenever SQI becomes worse than the threshold, link failure count (Register 0x0561 bit[9:0]) as defined by TC1 is incremented |
TC1_LINK_FAIL_LOSS is shown in Figure 8-76 and described in Table 8-83.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| link_losses | link_failures | ||||||
| R-0b | R-0b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| link_failures | |||||||
| R-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | link_losses | R | 0b | Number of Link Losses occurred since last power cycle (as per TC1 specification) |
| 9-0 | link_failures | R | 0b | Number of Link Failures causing NOT a link loss since last power cycle (as per TC1 specification) |
TC1_LINK_TRAINING_TIME is shown in Figure 8-77 and described in Table 8-84.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| comm_ready | RESERVED | ||||||
| R-0b | R-0b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| lq_ltt | |||||||
| R-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | comm_ready | R | 0b | TC1 comm ready signal (Optimized link status indication for higher Layers to indicate if communication is possible via link)
0b = Communication Not Possible 1b = Communication Possible |
| 14-8 | RESERVED | R | 0b | Reserved |
| 7-0 | lq_ltt | R | 0b | Link training time of the last link training (as per TC1 specification) |
RGMII_CTRL is shown in Figure 8-78 and described in Table 8-85.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | rgmii_tx_half_full_th | cfg_rgmii_en | inv_rgmii_txd | inv_rgmii_rxd | sup_tx_err_fd_rgmii | ||
| R-0b | R/W-11b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-7 | RESERVED | R | 0b | Reserved |
| 6-4 | rgmii_tx_half_full_th | R/W | 11b | RGMII TX sync FIFO half full threshold in number if nibbles |
| 3 | cfg_rgmii_en | R/W | 0b | RGMII enable bit
Default from strap
if(RX_D2_strap == 1)
reset_val = 1
else
reset_val = 0
0b = RGMII disable 1b = RGMII enable |
| 2 | inv_rgmii_txd | R/W | 0b | Invert RGMII Tx wire order - full swap [3:0] -- [0:3] |
| 1 | inv_rgmii_rxd | R/W | 0b | Invert RGMII Rx wire order - full swap [3:0] -- [0:3] |
| 0 | sup_tx_err_fd_rgmii | R/W | 0b | this bit can disable the TX_ERR indication input |
RGMII_FIFO_STATUS is shown in Figure 8-79 and described in Table 8-86.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | rgmii_tx_af_full_err | rgmii_tx_af_empty_err | |||||
| R-0b | R-0b | R-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-2 | RESERVED | R | 0b | Reserved |
| 1 | rgmii_tx_af_full_err | R | 0b | RGMII Tx fifo full error |
| 0 | rgmii_tx_af_empty_err | R | 0b | RGMII Tx fifo empty error |
RGMII_CLK_SHIFT_CTRL is shown in Figure 8-80 and described in Table 8-87.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_rgmii_rx_clk_shift_sel | cfg_rgmii_tx_clk_shift_sel | |||||
| R-0b | R/W-0b | R/W-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-2 | RESERVED | R | 0b | Reserved |
| 1 | cfg_rgmii_rx_clk_shift_sel | R/W | 0b | 0: clock and data are aligned
1: clock on PIN is delayed by 90 degrees relative to RGMII_RX data
if({RX_D2_strap, RX_D1_strap} == 2'b11)
reset_val = 1
else
resett_val = 0
0b = clock and data are aligned 1b = clock on PIN is delayed by 90 degrees relative to RGMII_RX data |
| 0 | cfg_rgmii_tx_clk_shift_sel | R/W | 0b | use this mode when RGMII_TX_CLK and RGMII_TXD are aligned if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b101) reset_val = 1 else if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b110) reset_val = 1 else reset_val = 0 |
RGMII_EEE_CTRL is shown in Figure 8-81 and described in Table 8-88.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_rgmii_wake_signaling_en | ||||||
| R-0b | R/W-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-2 | RESERVED | R | 0b | Reserved |
| 1-0 | cfg_rgmii_wake_signaling_en | R/W | 0b | RGMII signaling behavior during exit LPI period. Bit[1] - exhibit rx_err on rx_ctrl for lpi_exit, else rx_ctrl is zero for both lpi and exit_lpi periods. Bit[0] - exhibit zeros on rxd for lpi_exit, else rxd=IB_code Note: option 00b is not supported, non-valid coding. |
SGMII_CTRL_1 is shown in Figure 8-82 and described in Table 8-89.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| sgmii_tx_err_dis | cfg_align_idx_force_en | cfg_align_idx_value | cfg_sgmii_en | cfg_sgmii_rx_pol_invert | |||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_sgmii_tx_pol_invert | serdes_tx_bits_order | serdes_rx_bits_order | cfg_sgmii_align_pkt_en | sgmii_autoneg_timer | sgmii_autoneg_en | ||
| R/W-0b | R/W-11b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | sgmii_tx_err_dis | R/W | 0b | SGMII TX err disable bit |
| 14 | cfg_align_idx_force_en | R/W | 0b | Force word boundray index selection |
| 13-10 | cfg_align_idx_value | R/W | 0b | when cfg_align_idx_force is set,This value set the iword boundray index |
| 9 | cfg_sgmii_en | R/W | 0b | SGMII enable bit
Default from strap
if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b000)
reset_val = 1
else
reset_val = 0
0b = SGMII MAC i/f disabled 1b = SGMII MAC i/f enabled |
| 8 | cfg_sgmii_rx_pol_invert | R/W | 0b | SGMII RX bus invert polarity |
| 7 | cfg_sgmii_tx_pol_invert | R/W | 0b | SGMII TX bus invert polarity |
| 6-5 | serdes_tx_bits_order | R/W | 11b | SERDES TX bits order (input to digital core) |
| 4 | serdes_rx_bits_order | R/W | 1b | SERDES RX bits order (output of digital core) : 0 - MSB-first (default) 1 - LSB-first (reversed order) |
| 3 | cfg_sgmii_align_pkt_en | R/W | 1b | For aligning the start of read out TX packet (towards serializer) w/ tx_even pulse. To sync with the Code_Group/OSET FSM code slots. Default is '1', when using '0' we go back to Gemini code |
| 2-1 | sgmii_autoneg_timer | R/W | 1b | Selects duration of SGMII Auto-Negotiation timer
0b = 1.6ms 1b = 2us 10b = 800us 11b = 11ms |
| 0 | sgmii_autoneg_en | R/W | 1b | sgmii auto negotiation enable
0b = SGMII autoneg disabled 1b = SGMII autoneg enabled |
SGMII_EEE_CTRL_1 is shown in Figure 8-83 and described in Table 8-90.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_sgmii_tx_tr_timer_val | cfg_sgmii_tx_tq_timer_val | ||||||
| R/W-0b | R/W-0b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_sgmii_tx_tq_timer_val | cfg_sgmii_tx_ts_timer_val | cfg_support_non_eee_mac_sgmii_en | |||||
| R/W-0b | R/W-0b | R/W-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | cfg_sgmii_tx_tr_timer_val | R/W | 0b | |
| 10-6 | cfg_sgmii_tx_tq_timer_val | R/W | 0b | |
| 5-1 | cfg_sgmii_tx_ts_timer_val | R/W | 0b | |
| 0 | cfg_support_non_eee_mac_sgmii_en | R/W | 0b | special mode to support non sgmii eee mac in eee mode in the phy |
SGMII_STATUS is shown in Figure 8-84 and described in Table 8-91.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | sgmii_page_received | link_status_1000bx | sgmii_autoneg_complete | cfg_align_en | cfg_sync_status | ||
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_align_idx | RESERVED | ||||||
| R-0b | R-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | RESERVED | R | 0b | Reserved |
| 12 | sgmii_page_received | R | 0b | Clear on read bit. Indicates that a new auto neg page was received |
| 11 | link_status_1000bx | R | 0b | sgmii link status
0b = SGMII link is down 1b = SGMII link is up |
| 10 | sgmii_autoneg_complete | R | 0b | sgmii autoneg complete indication
0b = SGMII autoneg incomplete 1b = SGMII autoneg completed |
| 9 | cfg_align_en | R | 0b | word boundary FSM - align indication |
| 8 | cfg_sync_status | R | 0b | word boundary FSM - sync status indication |
| 7-4 | cfg_align_idx | R | 0b | word boundary index selection |
| 3-0 | RESERVED | R | 0b | Reserved |
SGMII_EEE_CTRL_2 is shown in Figure 8-85 and described in Table 8-92.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_sgmii_rx_quiet_timer_val | ||||||
| R-0b | R/W-101b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | RESERVED | R | 0b | Reserved |
| 3-0 | cfg_sgmii_rx_quiet_timer_val | R/W | 101b | Configures the RX Quiet Timer Value. Timer Value = (3100 + code*100)us |
SGMII_CTRL_2 is shown in Figure 8-86 and described in Table 8-93.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | sgmii_cdr_lock_force_val | ||||||
| R-0b | R/W-0b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sgmii_cdr_lock_force_ctrl | sgmii_mr_restart_an | tx_half_full_th | rx_half_full_th | ||||
| R/W-0b | RH/W1S-0b | R/W-100b | R/W-100b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-9 | RESERVED | R | 0b | Reserved |
| 8 | sgmii_cdr_lock_force_val | R/W | 0b | SGMII cdr lock force value |
| 7 | sgmii_cdr_lock_force_ctrl | R/W | 0b | SGMII cdr lock force enable |
| 6 | sgmii_mr_restart_an | RH/W1S | 0b | Restart sgmii autonegotiation |
| 5-3 | tx_half_full_th | R/W | 100b | SGMII TX sync FIFO half full threshold |
| 2-0 | rx_half_full_th | R/W | 100b | SGMII RX sync FIFO half full threshold |
SGMII_FIFO_STATUS is shown in Figure 8-87 and described in Table 8-94.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | sgmii_rx_af_full_err | sgmii_rx_af_empty_err | sgmii_tx_af_full_err | sgmii_tx_af_empty_err | |||
| R-0b | H-0b | H-0b | H-0b | H-0b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | RESERVED | R | 0b | Reserved |
| 3 | sgmii_rx_af_full_err | H | 0b | SGMII RX fifo full error
0b = No error indication 1b = SGMII RX fifo full error has been indicated |
| 2 | sgmii_rx_af_empty_err | H | 0b | SGMII RX fifo empty error
0b = No error indication 1b = SGMII RX fifo empty error has been indicated |
| 1 | sgmii_tx_af_full_err | H | 0b | SGMII TX fifo full error
0b = No error indication 1b = SGMII TX fifo full error has been indicated |
| 0 | sgmii_tx_af_empty_err | H | 0b | SGMII TX fiff empty error
0b = No error indication 1b = SGMII TX fifo empty error has been indicated |
PRBS_STATUS_1 is shown in Figure 8-88 and described in Table 8-95.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| prbs_err_ov_cnt | |||||||
| R-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | RESERVED | R | 0b | Reserved |
| 7-0 | prbs_err_ov_cnt | R | 0b | Holds number of error counter overflow that received by the PRBS checker. Value in this register is locked when write is done to register 0x001B bit[0] or bit[1]. Counter stops on 0xFF. Note: when PRBS counters work in single mode, overflow counter is not active |
PRBS_CTRL_1 is shown in Figure 8-89 and described in Table 8-96.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_pkt_gen_64 | send_pkt | RESERVED | cfg_prbs_chk_sel | |||
| R-0b | R/W-0b | RH/W1S-0b | R-0b | R/W-101b | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | cfg_prbs_gen_sel | cfg_prbs_cnt_mode | cfg_prbs_chk_enable | cfg_pkt_gen_prbs | pkt_gen_en | ||
| R-0b | R/W-111b | R/W-0b | R/W-1b | R/W-0b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | RESERVED | R | 0b | Reserved |
| 13 | cfg_pkt_gen_64 | R/W | 0b | 0b = Transmit 1518 byte packets in packet generation mode 1b = Transmit 64 byte packets in packet generation mode |
| 12 | send_pkt | RH/W1S | 0b | Enables generating MAC packet with fix/incremental data w CRC (pkt_gen_en has to be set and cfg_pkt_gen_prbs has to be clear) Cleared automatically when pkt_done is set |
| 11 | RESERVED | R | 0b | Reserved |
| 10-8 | cfg_prbs_chk_sel | R/W | 101b | 000 : Checker receives from RGMII TX 001 : Checker receives from SGMII TX 010 : Checker receives from RMII RX 011 : Checker receives from MII 101 : Checker receives from Cu RX 110 : Reserved 111 : Reserved |
| 7 | RESERVED | R | 0b | Reserved |
| 6-4 | cfg_prbs_gen_sel | R/W | 111b | 000 : PRBS transmits to RGMII RX 001 : PRBS transmits to SGMII RX 010 : PRBS transmits to RMII RX 011 : PRBS transmits to MII RX 101 : PRBS transmits to Cu TX 110 : Reserved 111 : Reserved |
| 3 | cfg_prbs_cnt_mode | R/W | 0b | 0b = Single mode, When one of the PRBS counters reaches max value, PRBS checker stops counting. 1b = Continuous mode, when one of the PRBS counters reaches max value, pulse is generated and counter starts counting from zero again |
| 2 | cfg_prbs_chk_enable | R/W | 1b | Enable PRBS checker |
| 1 | cfg_pkt_gen_prbs | R/W | 0b | If set: (1) When pkt_gen_en is set, PRBS packets are generated continuously (3) When pkt_gen_en is cleared, PRBS RX checker is still enabled If cleared: (1) When pkt_gen_en is set, non - PRBS packet is generated (3) When pkt_gen_en is cleared, PRBS RX checker is disabled as well |
| 0 | pkt_gen_en | R/W | 0b | Enable/disable for prbs/packet generator
0b = Disable for prbs/packet generator 1b = Enable for prbs/packet generator |
PRBS_CTRL_2 is shown in Figure 8-90 and described in Table 8-97.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_pkt_len_prbs | |||||||
| R/W-10111011100b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_pkt_len_prbs | |||||||
| R/W-10111011100b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | cfg_pkt_len_prbs | R/W | 10111011100b | Length (in bytes) of PRBS packets and MAC packets w CRC |
PRBS_CTRL_3 is shown in Figure 8-91 and described in Table 8-98.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_ipg_len | |||||||
| R/W-1111101b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | RESERVED | R | 0b | Reserved |
| 7-0 | cfg_ipg_len | R/W | 1111101b | Inter-packet gap (in bytes) between packets |
PRBS_STATUS_2 is shown in Figure 8-92 and described in Table 8-99.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| prbs_byte_cnt | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| prbs_byte_cnt | |||||||
| R-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | prbs_byte_cnt | R | 0b | Holds number of total bytes that received by the PRBS checker. Value in this register is locked when write is done to register 0x001B bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFF |
PRBS_STATUS_3 is shown in Figure 8-93 and described in Table 8-100.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| prbs_pkt_cnt_15_0 | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| prbs_pkt_cnt_15_0 | |||||||
| R-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | prbs_pkt_cnt_15_0 | R | 0b | Bits [15:0] of number of total packets received by the PRBS checker Value in this register is locked when write is done to register 0x001B bit[15] or bit[14]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF |
PRBS_STATUS_4 is shown in Figure 8-94 and described in Table 8-101.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| prbs_pkt_cnt_31_16 | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| prbs_pkt_cnt_31_16 | |||||||
| R-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | prbs_pkt_cnt_31_16 | R | 0b | Bits [31:16] of number of total packets received by the PRBS checker Value in this register is locked when write is done to register 0x001B bit[15] or bit[14]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF |
PRBS_STATUS_5 is shown in Figure 8-95 and described in Table 8-102.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | pkt_done | pkt_gen_busy | prbs_pkt_ov | prbs_byte_ov | prbs_lock | ||
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| prbs_err_cnt | |||||||
| R-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | RESERVED | R | 0b | Reserved |
| 12 | pkt_done | R | 0b | Set when all MAC packets w CRC are transmitted |
| 11 | pkt_gen_busy | R | 0b | status of packet generator |
| 10 | prbs_pkt_ov | R | 0b | If set, packet counter reached overflow Overflow is cleared when PRBS counters are cleared - done by setting bit[15] of 0x001B |
| 9 | prbs_byte_ov | R | 0b | If set, bytes counter reached overflow Overflow is cleared when PRBS counters are cleared - done by setting bit[15] of 0x001B |
| 8 | prbs_lock | R | 0b | prbs lock status |
| 7-0 | prbs_err_cnt | R | 0b | Holds number of errored bytes that received by the PRBS checker Value in this register is locked when write is done to bit[0] or bit[1] When PRBS Count Mode set to zero, count stops on 0xFF Notes: Writing bit 0 generates a lock signal for the PRBS counters. Writing bit 1 generates a lock and clear signal for the PRBS counters |
PRBS_STATUS_6 is shown in Figure 8-96 and described in Table 8-103.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pkt_err_cnt_15_0 | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pkt_err_cnt_15_0 | |||||||
| R-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | pkt_err_cnt_15_0 | R | 0b | bits [15:0] of counter which records number or PRBS erroneous bytes received. This field gets cleared when bit[15] or bit[14] is written as 1 to register 0x001B |
PRBS_STATUS_7 is shown in Figure 8-97 and described in Table 8-104.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pkt_err_cnt_31_16 | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pkt_err_cnt_31_16 | |||||||
| R-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | pkt_err_cnt_31_16 | R | 0b | bits [31:16] of counter which records number or PRBS erroneous bytes received. This field gets cleared when bit[15] or bit[14] is written as 1 to register 0x001B |
PRBS_CTRL_4 is shown in Figure 8-98 and described in Table 8-105.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| cfg_pkt_data | |||||||
| R/W-1010101b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_pkt_mode | cfg_pattern_vld_bytes | cfg_pkt_cnt | |||||
| R/W-0b | R/W-10b | R/W-1b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | cfg_pkt_data | R/W | 1010101b | Fixed data to be sent in Fix data mode |
| 7-6 | cfg_pkt_mode | R/W | 0b | Selects the type of data sent
0b = Incremental Data 1b = Fixed Data 10b = PRBS Data (Random Data) 11b = PRBS Data (Random Data) |
| 5-3 | cfg_pattern_vld_bytes | R/W | 10b | Number of bytes of valid pattern in packet (Max - 6) |
| 2-0 | cfg_pkt_cnt | R/W | 1b | Configures the number of MAC packets to be transmitted by packet generator
0b = 1 packet 1b = 10 packets 10b = 100 packets 11b = 1000 packets 100b = 10000 packets 101b = 100000 packets 110b = 1000000 packets 111b = Continuous packets |
PATTERN_CTRL_1 is shown in Figure 8-99 and described in Table 8-106.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pattern_15_0 | |||||||
| R/W-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pattern_15_0 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | pattern_15_0 | R/W | 0b | Bits 15:0 of pattern |
PATTERN_CTRL_2 is shown in Figure 8-100 and described in Table 8-107.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pattern_31_16 | |||||||
| R/W-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pattern_31_16 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | pattern_31_16 | R/W | 0b | Bits 31:16 of pattern |
PATTERN_CTRL_3 is shown in Figure 8-101 and described in Table 8-108.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pattern_47_32 | |||||||
| R/W-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pattern_47_32 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | pattern_47_32 | R/W | 0b | Bits 47:32 of pattern |
PMATCH_CTRL_1 is shown in Figure 8-102 and described in Table 8-109.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pmatch_data_15_0 | |||||||
| R/W-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pmatch_data_15_0 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | pmatch_data_15_0 | R/W | 0b | Bits 15:0 of Perfect Match Data - used for DA (destination address) match |
PMATCH_CTRL_2 is shown in Figure 8-103 and described in Table 8-110.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pmatch_data_31_16 | |||||||
| R/W-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pmatch_data_31_16 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | pmatch_data_31_16 | R/W | 0b | Bits 31:16 of Perfect Match Data - used for DA (destination address) match |
PMATCH_CTRL_3 is shown in Figure 8-104 and described in Table 8-111.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| pmatch_data_47_32 | |||||||
| R/W-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| pmatch_data_47_32 | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | pmatch_data_47_32 | R/W | 0b | Bits 47:32 of Perfect Match Data - used for DA (destination address) match |
TX_PKT_CNT_1 is shown in Figure 8-105 and described in Table 8-112.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| tx_pkt_cnt_15_0 | |||||||
| 0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| tx_pkt_cnt_15_0 | |||||||
| 0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | tx_pkt_cnt_15_0 | 0b | Lower 16 bits of Tx packet counter Note : Register is cleared when 0x60F, 0x610, 0x611 are read in sequence |
TX_PKT_CNT_2 is shown in Figure 8-106 and described in Table 8-113.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| tx_pkt_cnt_31_16 | |||||||
| 0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| tx_pkt_cnt_31_16 | |||||||
| 0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | tx_pkt_cnt_31_16 | 0b | Upper 16 bits of Tx packet counter Note : Register is cleared when 0x60F, 0x610, 0x611 are read in sequence |
TX_PKT_CNT_3 is shown in Figure 8-107 and described in Table 8-114.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| tx_err_pkt_cnt | |||||||
| 0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| tx_err_pkt_cnt | |||||||
| 0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | tx_err_pkt_cnt | 0b | Tx packet w error (CRC error) counter Note : Register is cleared when 0x60F, 0x610, 0x611 are read in sequence |
RX_PKT_CNT_1 is shown in Figure 8-108 and described in Table 8-115.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| rx_pkt_cnt_15_0 | |||||||
| 0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| rx_pkt_cnt_15_0 | |||||||
| 0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | rx_pkt_cnt_15_0 | 0b | Lower 16 bits of Rx packet counter Note : Register is cleared when 0x612, 0x613, 0x614 are read in sequence |
RX_PKT_CNT_2 is shown in Figure 8-109 and described in Table 8-116.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| rx_pkt_cnt_31_16 | |||||||
| 0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| rx_pkt_cnt_31_16 | |||||||
| 0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | rx_pkt_cnt_31_16 | 0b | Upper 16 bits of Rx packet counter Note : Register is cleared when 0x612, 0x613, 0x614 are read in sequence |
RX_PKT_CNT_3 is shown in Figure 8-110 and described in Table 8-117.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| rx_err_pkt_cnt | |||||||
| 0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| rx_err_pkt_cnt | |||||||
| 0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | rx_err_pkt_cnt | 0b | Rx packet w error (CRC error) counter Note : Register is cleared when 0x612, 0x613, 0x614 are read in sequence |
RMII_CTRL_1 is shown in Figure 8-111 and described in Table 8-118.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_rmii_dis_delayed_txd_en | cfg_rmii_half_full_th | |||||
| R-0b | R/W-0b | R/W-10b | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| cfg_rmii_half_full_th | cfg_rmii_mode | cfg_rmii_bypass_afifo_en | cfg_xi_50 | RESERVED | RESERVED | cfg_rmii_rev1_0 | cfg_rmii_enh |
| R/W-10b | R/W-0b | R/W-1b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0b | Reserved |
| 10 | cfg_rmii_dis_delayed_txd_en | R/W | 0b | If set, disables delay of TXD in RMII mode |
| 9-7 | cfg_rmii_half_full_th | R/W | 10b | FIFO Half Full Threshold in nibbles for the RMII Rx FIFO |
| 6 | cfg_rmii_mode | R/W | 0b | 1 = RMII enabled
0 = RMII disabled
if({RX_D2_strap, RX_D1_strap} == 2'b01)
reset_val = 1
else
reset_val = 0
0b = RMII disabled 1b = RMII enabled |
| 5 | cfg_rmii_bypass_afifo_en | R/W | 1b | 1= RMII async fifo bypass enable
0= RMII async fifo not bypassed
0b = RMII async fifo not bypassed 1b = RMII async fifo bypass enable |
| 4 | cfg_xi_50 | R/W | 0b | XI sel for RMII mode if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b010) reset_val = 1 else reset_val = 0 |
| 3 | RESERVED | R/W | 0b | Reserved |
| 2 | RESERVED | R/W | 0b | Reserved |
| 1 | cfg_rmii_rev1_0 | R/W | 0b | RMII Rev1.0 enable bit |
| 0 | cfg_rmii_enh | R/W | 0b | RMII enahnced mode enable bit |
RMII_STATUS_1 is shown in Figure 8-112 and described in Table 8-119.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | rmii_af_unf_err | rmii_af_ovf_err | |||||
| R-0b | R-0b | R-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-2 | RESERVED | R | 0b | Reserved |
| 1 | rmii_af_unf_err | R | 0b | Clear on read bit RMII fifo undeflow error status |
| 0 | rmii_af_ovf_err | R | 0b | Clear on Read bit RMII fifo overflow status |
RMII_OVERRIDE_CTRL is shown in Figure 8-113 and described in Table 8-120.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | cfg_clk50_tx_dll | cfg_clk50_dll | RESERVED | ||||
| R-0b | R/W-0b | R/W-0b | R/W-0b | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
| R/W-0b | R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0b | Reserved |
| 10 | cfg_clk50_tx_dll | R/W | 0b | 1 = use 50M DLL clock in RMII master for TX
0 = legacy mode
if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b011)
reset_val = 1
else
reset_val = 0
0b = legacy mode 1b = use 50M DLL clock in RMII master for TX |
| 9 | cfg_clk50_dll | R/W | 0b | 1 = use 50M DLL clock in RMII slave for RX
0 = use legacy mode
if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b010)
reset_val = 1
else
reset_val = 0
0b = use legacy mode 1b = use 50M DLL clock in RMII slave for RX |
| 8 | RESERVED | R/W | 0b | Reserved |
| 7 | RESERVED | R/W | 0b | Reserved |
| 6 | RESERVED | R/W | 0b | Reserved |
| 5 | RESERVED | R/W | 0b | Reserved |
| 4 | RESERVED | R/W | 1b | Reserved |
| 3 | RESERVED | R/W | 0b | Reserved |
| 2 | RESERVED | R/W | 0b | Reserved |
| 1 | RESERVED | R/W | 0b | Reserved |
| 0 | RESERVED | R/W | 0b | Reserved |
dsp_reg_71 is shown in Figure 8-114 and described in Table 8-121.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| worst_sqi_out | RESERVED | sqi_out | RESERVED | ||||
| 0b | R-0b | R-0b | R-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | RESERVED | R | 0b | Reserved |
| 7-5 | worst_sqi_out | 0b | Worst SQI value since last read | |
| 4 | RESERVED | R | 0b | Reserved |
| 3-1 | sqi_out | R | 0b | SQI value |
| 0 | RESERVED | R | 0b | Reserved |
MMD1_PMA_CTRL_1 is shown in Figure 8-115 and described in Table 8-122.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PMA_reset | RESERVED | ||||||
| R/W-0b | R-0b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PMA_loopback | ||||||
| R-0b | R/W-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | PMA_reset | R/W | 0b | 0 = PMA not reset
1= PMA reset
0b = PMA not reset 1b = PMA reset |
| 14-1 | RESERVED | R | 0b | Reserved |
| 0 | PMA_loopback | R/W | 0b | 0 = PMA loopback not set
1= PMA loopback set
0b = PMA loopback not set 1b = PMA loopback set |
MMD1_PMA_STATUS_1 is shown in Figure 8-116 and described in Table 8-123.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | link_status | RESERVED | |||||
| R-0b | R-0b | R-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-3 | RESERVED | R | 0b | Reserved |
| 2 | link_status | R | 0b | link status from link monitor state machine
0b = link status is down 1b = link status is up |
| 1-0 | RESERVED | R | 0b | Reserved |
MMD1_PMA_STAUS_2 is shown in Figure 8-117 and described in Table 8-124.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PMA/PMD type selection | ||||||
| R-0b | R-111101b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-6 | RESERVED | R | 0b | Reserved |
| 5-0 | PMA/PMD type selection | R | 111101b | PMA or PMD type selection field 11111xb = reserved for future use 111100b = reserved for future use 1110xxb = reserved for future use 110xxxb = reserved for future use 111101b = 100BASE-T1 PMA or PMD |
MMD1_PMA_EXT_ABILITY_1 is shown in Figure 8-118 and described in Table 8-125.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | BASE-T1 extended abilities | RESERVED | |||||
| R-0b | R-1b | R-0b | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | RESERVED | R | 0b | Reserved |
| 11 | BASE-T1 extended abilities | R | 1b | 1 = PMA/PMD has BASE-T1 extended abilities listed in register 18 in MMD1
0 = PMA/PMD does not have BASE-T1 extended abilities
0b = PMA/PMD does not have BASE-T1 extended abilities 1b = PMA/PMD has BASE-T1 extended abilities listed in register 18 in MMD1 |
| 10-0 | RESERVED | R | 0b | Reserved |
MMD1_PMA_EXT_ABILITY_2 is shown in Figure 8-119 and described in Table 8-126.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0b | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | 100BASE-T1 ability | ||||||
| R-0b | R-1b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-1 | RESERVED | R | 0b | Reserved |
| 0 | 100BASE-T1 ability | R | 1b | 1 = PMA/PMD is able to perform 100BASE-T1
0 = PMA/PMD is not able to perform 100BASE-T1
0b = PMA/PMD is not able to perform 100BASE-T1 1b = PMA/PMD is able to perform 100BASE-T1 |
MMD1_PMA_CTRL_2 is shown in Figure 8-120 and described in Table 8-127.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| master_slave_man_cfg_en | brk_ms_cfg | RESERVED | |||||
| R-1b | R/W-0b | R-0b | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | type selection | ||||||
| R-0b | R-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | master_slave_man_cfg_en | R | 1b | Value always 1 |
| 14 | brk_ms_cfg | R/W | 0b | 1 = Configure PHY as MASTER
0 = Configure PHY as SLAVE
pkg_36:
reset_val = LED_0_strap
pkg_28:
reset_val = RX_D3_strap
0b = Configure PHY as SLAVE 1b = Configure PHY as MASTER |
| 13-4 | RESERVED | R | 0b | Reserved |
| 3-0 | type selection | R | 0b | type selection field
1xxxb = Reserved for future use
01xxb = Reserved for future use
001xb = Reserved for future use
0001b = Reserved for future use
0b = 100BASE-T1 |
MMD1_PMA_TEST_MODE_CTRL is shown in Figure 8-121 and described in Table 8-128.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| brk_test_mode | RESERVED | ||||||
| R/W-0b | R/W-0b | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R/W-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | brk_test_mode | R/W | 0b | 100BASE-T1 test mode control 000b = Normal mode operation 001b = Test mode 1 010b = Test mode 2 011b = Reserved 100b = Test mode 4 101b = Test mode 5 110b = Reserved 111b = Reserved |
| 12-0 | RESERVED | R/W | 0b | Reserved |
MMD3_PCS_CTRL_1 is shown in Figure 8-122 and described in Table 8-129.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PCS_Reset | PCS_loopback | RESERVED | rx_clock_stoppable | RESERVED | |||
| R/W-0b | R/W-0b | R-0b | R/W-0b | R-0b | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R-0b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | PCS_Reset | R/W | 0b | Reset bit, Self Clear. When write to this bit 1: 1. reset the registers (not vendor specific) at MMD3/MMD7. 2. Reset brk_top Please notice: This register is WSC (write-self-clear) and not read-only! |
| 14 | PCS_loopback | R/W | 0b | This bit is cleared by PCS_Reset |
| 13-11 | RESERVED | R | 0b | Reserved |
| 10 | rx_clock_stoppable | R/W | 0b | RW, reset value = 1. 1= PHY may stop receive clock during LPI 0= Clock not stoppable Note: this flop implemented at glue logic |
| 9-0 | RESERVED | R | 0b | Reserved |
MMD3_PCS_Status_1 is shown in Figure 8-123 and described in Table 8-130.
Return to the Summary Table.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | TX_LPI_received | RX_LPI_received | Tx_LPI_indication | Rx_LPI_indication | |||
| R-0b | R-0b | R-0b | R-0b | R-0b | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | tx_clock_stoppable | RESERVED | |||||
| R-0b | R-0b | R-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | RESERVED | R | 0b | Reserved |
| 11 | TX_LPI_received | R | 0b | RO/LH
0b = LPI not received 1b = Tx PCS hs received LPI |
| 10 | RX_LPI_received | R | 0b | RO/LH
0b = LPI not received 1b = Rx PCS hs received LPI |
| 9 | Tx_LPI_indication | R | 0b | 1= TX PCS is currently receiving LPI
0= PCS is not currently receiving LPI
0b = PCS is not currently receiving LPI 1b = TX PCS is currently receiving LPI |
| 8 | Rx_LPI_indication | R | 0b | 1= RX PCS is currently receiving LPI
0= PCS is not currently receiving LPI
0b = PCS is not currently receiving LPI 1b = RX PCS is currently receiving LPI |
| 7 | RESERVED | R | 0b | Reserved |
| 6 | tx_clock_stoppable | R | 0b | 1= the MAC may stop the clock during LPI
0= Clock not stoppable
0b = Clock not stoppable 1b = the MAC may stop the clock during LPI |
| 5-0 | RESERVED | R | 0b | Reserved |