JAJSON9 May 2022 DP83TC813R-Q1 , DP83TC813S-Q1
PRODUCTION DATA
The Media Independent Interface (MII) is a synchronous 4-bit wide nibble data interface that connects the PHY to the MAC. The MII is fully compliant with IEEE 802.3-2015 clause 22. The PHY has internal series termination resistors on MII output pins including TX_CLK output when the PHY is operating in MII mode. In this mode, it is recommended to not leave the MII-TX pins floating or High-Z.
The MII signals are summarized in Table 8-4:
FUNCTION | PINS |
---|---|
Data Signals | TX_D[3:0] |
RX_D[3:0] | |
Control Signals | TX_EN, TX_ER |
RX_DV, RX_ER | |
Clock Signals | TX_CLK |
RX_CLK |
TX_EN | TX_ER | TX_D[3:0] | DESCRIPTION |
---|---|---|---|
0 | 0 | 0000 through 1111 | Normal Inter-Frame |
0 | 1 | 0000 through 1111 | Reserved |
1 | 0 | 0000 through 1111 | Normal Data Transmission |
1 | 1 | 0000 through 1111 | Transmit Error Propagation |
RX_DV | RX_ER | RX_D[3:0] | DESCRIPTION |
---|---|---|---|
0 | 0 | 0000 through 1111 | Normal Inter-Frame |
0 | 1 | 0000 | Normal Inter-Frame |
0 | 1 | 0001 through 1101 | Reserved |
0 | 1 | 1110 | False Carrier Indication |
0 | 1 | 1111 | Reserved |
1 | 0 | 0000 through 1111 | Normal Data Reception |
1 | 1 | 0000 through 1111 | Data Reception with Errors |