JAJSJF3 December 2021 DP83TC814R-Q1 , DP83TC814S-Q1
PRODUCTION DATA
The DP83TC814S-Q1 is capable of operating with a wide range of IO supply voltages (3.3 V, 2.5 V, or 1.8 V). No power supply sequencing is required. The recommended power supply de-coupling network is shown in the figure below. For improved conducted emissions, an optional ferrite bead may be placed between the supply and the PHY de-coupling network.
Typical application block diagram along with supply and peripherals is shown below.
When VDDIO and VDDMAC are separate, both voltage rails should have a dedicated network of ferrite bead, 0.47uF, and 0.01uF capacitors.
The following table highlights the break down of power consumption in active mode for each supply rail, specifically highlighting the split between VDDMAC and VDDIO.
VOLTAGE RAIL | VOLTAGE (V) | MAX CURRENT (mA)1 |
---|---|---|
MII | ||
VDDA | 3.3 | 63 |
VDDIO | 3.3 | 4 |
2.5 | 3 | |
1.8 | 2 | |
VDDMAC | 3.3 | 20 |
2.5 | 15 | |
1.8 | 11 | |
VDDA (pin #7) |
3.3 | 2 |
RMII | ||
VDDA | 3.3 | 63 |
VDDIO | 3.3 | 6 |
2.5 | 4 | |
1.8 | 3 | |
VDDMAC | 3.3 | 17 |
2.5 | 13 | |
1.8 | 10 | |
VDDA (pin #7) |
3.3 | 2 |
RGMII | ||
VDDA | 3.3 | 63 |
VDDIO | 3.3 | 4 |
2.5 | 3 | |
1.8 | 2 | |
VDDMAC | 3.3 | 17 |
2.5 | 13 | |
1.8 | 10 | |
VDDA (pin #7) |
3.3 | 2 |
SGMII | ||
VDDA | 3.3 | 95 |
VDDIO | 3.3 | 4 |
2.5 | 3 | |
1.8 | 2 | |
VDDMAC | 3.3 | 8 |
2.5 | 6 | |
1.8 | 4 | |
VDDA (pin #7) |
3.3 | 2 |