JAJSFR7F June   2016  – May 2019 DRA710 , DRA712 , DRA714 , DRA716 , DRA718

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  CSI2
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  HDQ1W
      10. 4.3.10 UART
      11. 4.3.11 McSPI
      12. 4.3.12 QSPI
      13. 4.3.13 McASP
      14. 4.3.14 USB
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 ATL
      25. 4.3.25 Emulation and Debug Subsystem
      26. 4.3.26 System and Miscellaneous
        1. 4.3.26.1 Sysboot
        2. 4.3.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.3.26.3 System Direct Memory Access (SDMA)
        4. 4.3.26.4 Interrupt Controllers (INTC)
      27. 4.3.27 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power on Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS CSI2 DC Electrical Characteristics
      6. Table 5-11 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-12 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-13 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      USBPHY DC Electrical Characteristics
      10. 5.7.2      HDMIPHY DC Electrical Characteristics
      11. 5.7.3      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-14 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics for CBD Package
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.10.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RC On-die Oscillator Clock
        2. 5.10.4.2 Output Clocks
        3. 5.10.4.3 DPLLs, DLLs
          1. 5.10.4.3.1 DPLL Characteristics
          2. 5.10.4.3.2 DLL Characteristics
          3. 5.10.4.3.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  CSI2
          1. 5.10.6.6.1 CSI-2 MIPI D-PHY
        7. 5.10.6.7  EMIF
        8. 5.10.6.8  GPMC
          1. 5.10.6.8.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.8.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
        9. 5.10.6.9  Timers
        10. 5.10.6.10 I2C
          1. Table 5-56 Timing Requirements for I2C Input Timings
          2. Table 5-57 Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)
          3. Table 5-58 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        11. 5.10.6.11 HDQ1W
          1. 5.10.6.11.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.11.2 HDQ/1-Wire—1-Wire Mode
        12. 5.10.6.12 UART
          1. Table 5-63 Timing Requirements for UART
          2. Table 5-64 Switching Characteristics Over Recommended Operating Conditions for UART
        13. 5.10.6.13 McSPI
        14. 5.10.6.14 QSPI
        15. 5.10.6.15 McASP
          1. Table 5-71 Timing Requirements for McASP1
          2. Table 5-72 Timing Requirements for McASP2
          3. Table 5-73 Timing Requirements for McASP3/4/5/6/7/8
        16. 5.10.6.16 USB
          1. 5.10.6.16.1 USB1 DRD PHY
          2. 5.10.6.16.2 USB2 PHY
          3. 5.10.6.16.3 USB3 DRD ULPI—SDR—Slave Mode—12-pin Mode
        17. 5.10.6.17 PCIe
        18. 5.10.6.18 DCAN
          1. Table 5-91 Timing Requirements for DCANx Receive
          2. Table 5-92 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-93 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-94 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-95 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-96 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-101 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-102 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-103 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-104 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-108 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-109 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-111 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 MLB
        21. 5.10.6.21 eMMC/SD/SDIO
          1. 5.10.6.21.1 MMC1—SD Card Interface
            1. 5.10.6.21.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.21.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.21.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.21.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.21.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.21.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.21.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.21.2 MMC2 — eMMC
            1. 5.10.6.21.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.21.2.2 High-speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.21.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
            4. 5.10.6.21.2.4 High-speed JC64 DDR, 8-bit data
              1. Table 5-142 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
          3. 5.10.6.21.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.21.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.21.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.21.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.21.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.21.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        22. 5.10.6.22 GPIO
        23. 5.10.6.23 PRU-ICSS
          1. 5.10.6.23.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.23.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-164 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-165 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.23.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-166 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.23.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-167 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-168 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.23.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-169 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-170 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-171 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.23.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.23.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-172 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-173 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-174 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-175 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-176 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.23.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.23.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-177 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-178 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-179 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.23.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-180 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-181 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-182 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-183 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.23.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-184 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-185 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.23.5 PRU-ICSS IOSETs
          6. 5.10.6.23.6 PRU-ICSS Manual Functional Mapping
        24. 5.10.6.24 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-202 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-203 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-204 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-205 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 Trace Port Interface Unit (TPIU)
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  IVA
    6. 6.6  IPU
    7. 6.7  GPU
    8. 6.8  BB2D
    9. 6.9  PRU-ICSS
    10. 6.10 Memory Subsystem
      1. 6.10.1 EMIF
      2. 6.10.2 GPMC
      3. 6.10.3 ELM
      4. 6.10.4 OCMC
    11. 6.11 Interprocessor Communication
      1. 6.11.1 MailBox
      2. 6.11.2 Spinlock
    12. 6.12 Interrupt Controller
    13. 6.13 EDMA
    14. 6.14 Peripherals
      1. 6.14.1  VIP
      2. 6.14.2  DSS
      3. 6.14.3  Timers
        1. 6.14.3.1 General-Purpose Timers
        2. 6.14.3.2 32-kHz Synchronized Timer (COUNTER_32K)
        3. 6.14.3.3 Watchdog Timer
      4. 6.14.4  I2C
      5. 6.14.5  UART
        1. 6.14.5.1 UART Features
        2. 6.14.5.2 IrDA Features
        3. 6.14.5.3 CIR Features
      6. 6.14.6  McSPI
      7. 6.14.7  QSPI
      8. 6.14.8  McASP
      9. 6.14.9  USB
      10. 6.14.10 PCIe
      11. 6.14.11 DCAN
      12. 6.14.12 GMAC_SW
      13. 6.14.13 eMMC/SD/SDIO
      14. 6.14.14 GPIO
      15. 6.14.15 ePWM
      16. 6.14.16 eCAP
      17. 6.14.17 eQEP
    15. 6.15 On-chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 Power Regulators
        3. 7.5.2.3 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 PCIe Board Design and Layout Guidelines
        1. 7.5.5.1 PCIe Connections and Interface Compliance
          1. 7.5.5.1.1 Coupling Capacitors
          2. 7.5.5.1.2 Polarity Inversion
        2. 7.5.5.2 Non-standard PCIe connections
          1. 7.5.5.2.1 PCB Stackup Specifications
          2. 7.5.5.2.2 Routing Specifications
            1. 7.5.5.2.2.1 Impedance
            2. 7.5.5.2.2.2 Differential Coupling
            3. 7.5.5.2.2.3 Pair Length Matching
        3. 7.5.5.3 LJCB_REFN/P Connections
      6. 7.5.6 CSI2 Board Design and Routing Guidelines
        1. 7.5.6.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.6.1.1 General Guidelines
          2. 7.5.6.1.2 Length Mismatch Guidelines
            1. 7.5.6.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.6.1.3 Frequency-domain Specification Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7 DDR3 Board Design and Layout Guidelines
      1. 7.7.1 DDR3 General Board Layout Guidelines
      2. 7.7.2 DDR3 Board Design and Layout Guidelines
        1. 7.7.2.1  Board Designs
        2. 7.7.2.2  DDR3 EMIF
        3. 7.7.2.3  DDR3 Device Combinations
        4. 7.7.2.4  DDR3 Interface Schematic
          1. 7.7.2.4.1 32-Bit DDR3 Interface
          2. 7.7.2.4.2 16-Bit DDR3 Interface
        5. 7.7.2.5  Compatible JEDEC DDR3 Devices
        6. 7.7.2.6  PCB Stackup
        7. 7.7.2.7  Placement
        8. 7.7.2.8  DDR3 Keepout Region
        9. 7.7.2.9  Bulk Bypass Capacitors
        10. 7.7.2.10 High-Speed Bypass Capacitors
          1. 7.7.2.10.1 Return Current Bypass Capacitors
        11. 7.7.2.11 Net Classes
        12. 7.7.2.12 DDR3 Signal Termination
        13. 7.7.2.13 VREF_DDR Routing
        14. 7.7.2.14 VTT
        15. 7.7.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.7.2.15.1 Four DDR3 Devices
            1. 7.7.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.7.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.7.2.15.2 Two DDR3 Devices
            1. 7.7.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.7.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.7.2.15.3 One DDR3 Device
            1. 7.7.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.7.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.7.2.16 Data Topologies and Routing Definition
          1. 7.7.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.7.2.17 Routing Specification
          1. 7.7.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.7.2.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • CBD|538
サーマルパッド・メカニカル・データ
発注情報

5.5.3 Maximum Supported Frequency

Device modules either receive their clock directly from an external clock input, directly from a PLL, or from a PRCM. Table 5-5 lists the clock source options for each module on this device, along with the maximum frequency that module can accept. To ensure proper module functionality, the device PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table.

Table 5-5 Maximum Supported Frequency

MODULE CLOCK SOURCES
INSTANCE NAME INPUT CLOCK NAME CLOCK TYPE MAX. CLOCK ALLOWED (MHz) PRCM CLOCK NAME PLL / OSC / SOURCE CLOCK NAME PLL / OSC / SOURCE NAME
AES1 AES1_L3_CLK Int 266 L4SEC_L3_GICLK CORE_X2_CLK DPLL_CORE
AES2 AES2_L3_CLK Int 266 L4SEC_L3_GICLK CORE_X2_CLK DPLL_CORE
ATL ATL_ICLK_L3 Int 266 ATL_L3_GICLK CORE_X2_CLK DPLL_CORE
ATLPCLK Func 266 ATL_GFCLK CORE_X2_CLK DPLL_CORE
PER_ABE_X1_GFCLK DPLL_ABE
FUNC_32K_CLK OSC0
HDMI_CLK DPLL_HDMI
VIDEO1_CLK DPLL_VIDEO1
BB2D BB2D_FCLK Func 354.6 BB2D_GFCLK BB2D_GFCLK DPLL_CORE
BB2D_ICLK Int 266 DSS_L3_GICLK CORE_X2_CLK DPLL_CORE
COUNTER_32K COUNTER_32K_FCLK Func 0.032 FUNC_32K_CLK SYS_CLK1/610 OSC0
COUNTER_32K_ICLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
CTRL_MODULE_BANDGAP L3INSTR_TS_GCLK Int 4.8 L3INSTR_TS_GCLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
CTRL_MODULE_CORE L4CFG_L4_GICLK Int 133 L4CFG_L4_GICLK CORE_X2_CLK DPLL_CORE
CTRL_MODULE_WKUP WKUPAON_GICLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
DCAN1 DCAN1_FCLK Func 38.4 DCAN1_SYS_CLK SYS_CLK1 OSC0
SYS_CLK2 OSC1
DCAN1_ICLK Int 266 WKUPAON_GICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
DCAN2 DCAN2_FCLK Func 38.4 DCAN2_SYS_CLK SYS_CLK1 OSC0
DCAN2_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
DES3DES DES_CLK_L3 Int 266 L4SEC_L3_GICLK CORE_X2_CLK DPLL_CORE
DLL EMIF_DLL_FCLK Func EMIF_DLL_FCLK EMIF_DLL_GCLK EMIF_DLL_GCLK DPLL_DDR
DLL_AGING FCLK Int 38.4 L3INSTR_DLL_AGING_GCLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
DMM DMM_CLK Int 266 EMIF_L3_GICLK CORE_X2_CLK DPLL_CORE
DPLL_DEBUG SYSCLK Int 38.4 EMU_SYS_CLK SYS_CLK1 OSC0
DSP1 DSP1_FICLK Int & Func DSP_CLK DSP1_GFCLK DSP_GFCLK DPLL_DSP
DSS DSS_HDMI_CEC_CLK Func 0.032 HDMI_CEC_GFCLK SYS_CLK1/610 OSC0
DSS_HDMI_PHY_CLK Func 48 HDMI_PHY_GFCLK FUNC_192M_CLK DPLL_PER
DSS_CLK Func 192 DSS_GFCLK DSS_CLK DPLL_PER
HDMI_CLKINP Func 38.4 HDMI_DPLL_CLK SYS_CLK1 OSC0
SYS_CLK2 OSC1
DSS_L3_ICLK Int 266 DSS_L3_GICLK CORE_X2_CLK DPLL_CORE
VIDEO1_CLKINP Func 38.4 VIDEO1_DPLL_CLK SYS_CLK1 OSC0
SYS_CLK2 OSC1
VIDEO2_CLKINP Func 38.4 VIDEO2_DPLL_CLK SYS_CLK1 OSC0
SYS_CLK2 OSC1
DPLL_DSI1_A_CLK1 Func 209.3 N/A HDMI_CLK DPLL_HDMI
VIDEO1_CLKOUT1 DPLL_VIDEO1
DPLL_DSI1_B_CLK1 Func 209.3 N/A VIDEO1_CLKOUT3 DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
DPLL_ABE_X2_CLK DPLL_ABE
DPLL_DSI1_C_CLK1 Func 209.3 N/A HDMI_CLK DPLL_HDMI
VIDEO1_CLKOUT3 DPLL_VIDEO1
DPLL_HDMI_CLK1 Func 185.6 N/A HDMI_CLK DPLL_HDMI
DSS DISPC LCD1_CLK Func 209.3 N/A DPLL_DSI1_A_CLK1 See DSS data in the rows above
DSS_CLK
LCD2_CLK Func 209.3 N/A DPLL_DSI1_B_CLK1
DSS_CLK
LCD3_CLK Func 209.3 N/A DPLL_DSI1_C_CLK1
DSS_CLK
F_CLK Func 209.3 N/A DPLL_DSI1_A_CLK1
DPLL_DSI1_B_CLK1
DPLL_DSI1_C_CLK1
DSS_CLK
DPLL_HDMI_CLK1
EFUSE_CTRL_CUST ocp_clk Int 133 CUSTEFUSE_L4_GICLK CORE_X2_CLK DPLL_CORE
sys_clk Func 38.4 CUSTEFUSE_SYS_GFCLK SYS_CLK1 OSC0
ELM ELM_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
EMIF_OCP_FW L3_CLK Int 266 EMIF_L3_GICLK CORE_X2_CLK DPLL_CORE
EMIF_PHY1 EMIF_PHY1_FCLK Func DDR EMIF_PHY_GCLK EMIF_PHY_GCLK DPLL_DDR
EMIF1 EMIF1_ICLK Int 266 EMIF_L3_GICLK CORE_X2_CLK DPLL_CORE
GMAC_SW CPTS_RFT_CLK Func 266 GMAC_RFT_CLK PER_ABE_X1_GFCLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
CORE_X2_CLK DPLL_CORE
MAIN_CLK Int 125 GMAC_MAIN_CLK GMAC_250M_CLK DPLL_GMAC
MHZ_250_CLK Func 250 GMII_250MHZ_CLK GMII_250MHZ_CLK DPLL_GMAC
MHZ_5_CLK Func 5 RGMII_5MHZ_CLK GMAC_RMII_HS_CLK DPLL_GMAC
MHZ_50_CLK Func 50 RMII_50MHZ_CLK GMAC_RMII_HS_CLK DPLL_GMAC
RMII1_MHZ_50_CLK Func 50 RMII_50MHZ_CLK GMAC_RMII_HS_CLK DPLL_GMAC
RMII2_MHZ_50_CLK Func 50 RMII_50MHZ_CLK GMAC_RMII_HS_CLK DPLL_GMAC
GPIO1 GPIO1_ICLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
GPIO1_DBCLK Func 0.032 WKUPAON_SYS_GFCLK WKUPAON_32K_GFCLK OSC0
GPIO2 GPIO2_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
GPIO2_DBCLK Func 0.032 GPIO_GFCLK FUNC_32K_CLK OSC0
GPIO3 GPIO3_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
GPIO3_DBCLK Func 0.032 GPIO_GFCLK FUNC_32K_CLK OSC0
GPIO4 GPIO4_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
GPIO4_DBCLK Func 0.032 GPIO_GFCLK FUNC_32K_CLK OSC0
PIDBCLK Func 0.032 GPIO_GFCLK
GPIO5 GPIO5_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
GPIO5_DBCLK Func 0.032 GPIO_GFCLK FUNC_32K_CLK OSC0
PIDBCLK Func 0.032 GPIO_GFCLK
GPIO6 GPIO6_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
GPIO6_DBCLK Func 0.032 GPIO_GFCLK FUNC_32K_CLK OSC0
PIDBCLK Func 0.032 GPIO_GFCLK
GPIO7 GPIO7_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
GPIO7_DBCLK Func 0.032 GPIO_GFCLK FUNC_32K_CLK OSC0
PIDBCLK Func 0.032 GPIO_GFCLK
GPIO8 GPIO8_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
GPIO8_DBCLK Func 0.032 GPIO_GFCLK FUNC_32K_CLK OSC0
PIDBCLK Func 0.032 GPIO_GFCLK
GPMC GPMC_FCLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
GPU GPU_FCLK1 Func GPU_CLK GPU_CORE_GCLK CORE_GPU_CLK DPLL_CORE
PER_GPU_CLK DPLL_PER
GPU_GCLK DPLL_GPU
GPU_FCLK2 Func GPU_CLK GPU_HYD_GCLK CORE_GPU_CLK DPLL_CORE
PER_GPU_CLK DPLL_PER
GPU_GCLK DPLL_GPU
GPU_ICLK Int 266 GPU_L3_GICLK CORE_X2_CLK DPLL_CORE
HDMI PHY DSS_HDMI_PHY_CLK Func 38.4 HDMI_PHY_GFCLK FUNC_192M_CLK DPLL_PER
HDQ1W HDQ1W_ICLK Int & Func 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
HDQ1W_FCLK Func 12 PER_12M_GFCLK FUNC_192M_CLK DPLL_PER
I2C1 I2C1_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
I2C1_FCLK Func 96 PER_96M_GFCLK FUNC_192M_CLK DPLL_PER
I2C2 I2C2_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
I2C2_FCLK Func 96 PER_96M_GFCLK FUNC_192M_CLK DPLL_PER
I2C3 I2C3_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
I2C3_FCLK Func 96 PER_96M_GFCLK FUNC_192M_CLK DPLL_PER
I2C4 I2C4_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
I2C4_FCLK Func 96 PER_96M_GFCLK FUNC_192M_CLK DPLL_PER
I2C5 I2C5_ICLK Int 266 IPU_L3_GICLK CORE_X2_CLK DPLL_CORE
I2C5_FCLK Func 96 IPU_96M_GFCLK FUNC_192M_CLK DPLL_PER
I2C6 I2C6_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
I2C6_FCLK Func 96 IPU_96M_GFCLK FUNC_192M_CLK DPLL_PER
IEEE1500_2_OCP PI_L3CLK Int & Func 266 L3INIT_L3_GICLK CORE_X2_CLK DPLL_CORE
IPU1 IPU1_GFCLK Int & Func 425.6 IPU1_GFCLK DPLL_ABE_X2_CLK DPLL_ABE
CORE_IPU_ISS_BOOST_CLK DPLL_CORE
IPU2 IPU2_GFCLK Int & Func 425.6 IPU2_GFCLK CORE_IPU_ISS_BOOST_CLK DPLL_CORE
IVA IVA_GCLK Int IVA_GCLK IVA_GCLK IVA_GFCLK DPLL_IVA
KBD KBD_FCLK Func 0.032 WKUPAON_SYS_GFCLK WKUPAON_32K_GFCLK OSC0
PICLKKBD Func 0.032 WKUPAON_SYS_GFCLK
KBD_ICLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
PICLKOCP Int 38.4 WKUPAON_GICLK DPLL_ABE_X2_CLK DPLL_ABE
L3_INSTR L3_CLK Int L3_CLK L3INSTR_L3_GICLK CORE_X2_CLK DPLL_CORE
L3_MAIN L3_CLK1 Int L3_CLK L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
L3_CLK2 Int L3_CLK L3INSTR_L3_GICLK CORE_X2_CLK DPLL_CORE
L4_CFG L4_CFG_CLK Int 133 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
L4_PER1 L4_PER1_CLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
L4_PER2 L4_PER2_CLK Int 133 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
L4_PER3 L4_PER3_CLK Int 133 L4PER3_L3_GICLK CORE_X2_CLK DPLL_CORE
L4_WKUP L4_WKUP_CLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
MAILBOX1 MAILBOX1_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
MAILBOX2 MAILBOX2_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
MAILBOX3 MAILBOX3_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
MAILBOX4 MAILBOX4_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
MAILBOX5 MAILBOX5_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
MAILBOX6 MAILBOX6_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
MAILBOX7 MAILBOX7_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
MAILBOX8 MAILBOX8_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
MAILBOX9 MAILBOX9_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
MAILBOX10 MAILBOX10_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
MAILBOX11 MAILBOX11_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
MAILBOX12 MAILBOX12_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
MAILBOX13 MAILBOX13_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
McASP1 MCASP1_AHCLKR Func 100 MCASP1_AHCLKR ABE_24M_GFCLK DPLL_ABE
ABE_SYS_CLK OSC0
FUNC_24M_GFCLK DPLL_PER
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
MLB_CLK Module MLB
MLBP_CLK Module MLB
MCASP1_AHCLKX Func 100 MCASP1_AHCLKX ABE_24M_GFCLK DPLL_ABE
ABE_SYS_CLK OSC0
FUNC_24M_GFCLK DPLL_PER
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
MLB_CLK Module MLB
MLBP_CLK Module MLB
MCASP1_FCLK Func 192 MCASP1_AUX_GFCLK PER_ABE_X1_GFCLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
MCASP1_ICLK Int 266 IPU_L3_GICLK CORE_X2_CLK DPLL_CORE
McASP2 MCASP2_AHCLKR Func 100 MCASP2_AHCLKR ABE_24M_GFCLK DPLL_ABE
ABE_SYS_CLK OSC0
FUNC_24M_GFCLK DPLL_PER
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
MLB_CLK Module MLB
MLBP_CLK Module MLB
MCASP2_AHCLKX Func 100 MCASP2_AHCLKX ABE_24M_GFCLK DPLL_ABE
ABE_SYS_CLK OSC0
FUNC_24M_GFCLK DPLL_PER
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
MLB_CLK Module MLB
MLBP_CLK Module MLB
MCASP2_FCLK Func 192 MCASP2_AUX_GFCLK PER_ABE_X1_GFCLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
MCASP2_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
McASP3 MCASP3_AHCLKX Func 100 MCASP3_AHCLKX ABE_24M_GFCLK DPLL_ABE
ABE_SYS_CLK OSC0
FUNC_24M_GFCLK DPLL_PER
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
MLB_CLK Module MLB
MLBP_CLK Module MLB
MCASP3_FCLK Func 192 MCASP3_AUX_GFCLK PER_ABE_X1_GFCLK DPLL_ABE
VIDEO1_CLK DPLL_ABE
HDMI_CLK DPLL_HDMI
MCASP3_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
McASP4 MCASP4_AHCLKX Func 100 MCASP4_AHCLKX ABE_24M_GFCLK DPLL_ABE
ABE_SYS_CLK OSC0
FUNC_24M_GFCLK DPLL_PER
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
MLB_CLK Module MLB
MLBP_CLK Module MLB
MCASP4_FCLK Func 192 MCASP4_AUX_GFCLK PER_ABE_X1_GFCLK DPLL_ABE
VIDEO1_CLK DPLL_ABE
HDMI_CLK DPLL_HDMI
MCASP4_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
McASP5 MCASP5_AHCLKX Func 100 MCASP5_AHCLKX ABE_24M_GFCLK DPLL_ABE
ABE_SYS_CLK OSC0
FUNC_24M_GFCLK DPLL_PER
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
MLB_CLK Module MLB
MLBP_CLK Module MLB
MCASP5_FCLK Func 192 MCASP5_AUX_GFCLK PER_ABE_X1_GFCLK DPLL_ABE
VIDEO1_CLK DPLL_ABE
HDMI_CLK DPLL_HDMI
MCASP5_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
McASP6 MCASP6_AHCLKX Func 100 MCASP6_AHCLKX ABE_24M_GFCLK DPLL_ABE
FUNC_24M_GFCLK DPLL_PER
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
MLB_CLK Module MLB
MLBP_CLK Module MLB
ABE_SYS_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
MCASP6_FCLK Func 192 MCASP6_AUX_GFCLK PER_ABE_X1_GFCLK DPLL_ABE
VIDEO1_CLK DPLL_ABE
HDMI_CLK DPLL_HDMI
MCASP6_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
McASP7 MCASP7_AHCLKX Func 100 MCASP7_AHCLKX ABE_24M_GFCLK DPLL_ABE
ABE_SYS_CLK OSC0
FUNC_24M_GFCLK DPLL_PER
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
MLB_CLK Module MLB
MLBP_CLK Module MLB
MCASP7_FCLK Func 192 MCASP7_AUX_GFCLK PER_ABE_X1_GFCLK DPLL_ABE
VIDEO1_CLK DPLL_ABE
HDMI_CLK DPLL_HDMI
MCASP7_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
McASP8 MCASP8_AHCLKX Func 100 MCASP8_AHCLKX ABE_24M_GFCLK DPLL_ABE
ABE_SYS_CLK OSC0
FUNC_24M_GFCLK DPLL_PER
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
MLB_CLK Module MLB
MLBP_CLK Module MLB
MCASP8_FCLK Func 192 MCASP8_AUX_GFCLK PER_ABE_X1_GFCLK DPLL_ABE
VIDEO1_CLK DPLL_ABE
HDMI_CLK DPLL_HDMI
MCASP8_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
McSPI1 SPI1_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
SPI1_FCLK Func 48 PER_48M_GFCLK PER_48M_GFCLK DPLL_PER
McSPI2 SPI2_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
SPI2_FCLK Func 48 PER_48M_GFCLK PER_48M_GFCLK DPLL_PER
McSPI3 SPI3_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
SPI3_FCLK Func 48 PER_48M_GFCLK PER_48M_GFCLK DPLL_PER
McSPI4 SPI4_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
SPI4_FCLK Func 48 PER_48M_GFCLK PER_48M_GFCLK DPLL_PER
MLB_SS MLB_L3_ICLK Int 266 MLB_SHB_L3_GICLK CORE_X2_CLK DPLL_CORE
MLB_L4_ICLK Int 133 MLB_SPB_L4_GICLK CORE_X2_CLK DPLL_CORE
MLB_FCLK Func 266 MLB_SYS_L3_GFCLK CORE_X2_CLK DPLL_CORE
CSI2_0 CTRLCLK Int & Func 96 LVDSRX_96M_GFCLK FUNC_192M_CLK DPLL_PER
CAL_FCLK Int & Func 266 CAL_GICLK CORE_ISS_MAIN_CLK DPLL_CORE
L3_ICLK CM_CORE_AON
MMC1 MMC1_CLK_32K Func 0.032 L3INIT_32K_GFCLK FUNC_32K_CLK OSC0
MMC1_FCLK Func 192 MMC1_GFCLK FUNC_192M_CLK DPLL_PER
128 FUNC_256M_CLK DPLL_PER
MMC1_ICLK1 Int 266 L3INIT_L3_GICLK CORE_X2_CLK DPLL_CORE
MMC1_ICLK2 Int 133 L3INIT_L4_GICLK CORE_X2_CLK DPLL_CORE
MMC2 MMC2_CLK_32K Func 0.032 L3INIT_32K_GFCLK FUNC_32K_CLK OSC0
MMC2_FCLK Func 192 MMC2_GFCLK FUNC_192M_CLK DPLL_PER
128 FUNC_256M_CLK DPLL_PER
MMC2_ICLK1 Int 266 L3INIT_L3_GICLK CORE_X2_CLK DPLL_CORE
MMC2_ICLK2 Int 133 L3INIT_L4_GICLK CORE_X2_CLK DPLL_CORE
MMC3 MMC3_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
MMC3_CLK_32K Func 0.032 L4PER_32K_GFCLK FUNC_32K_CLK OSC0
MMC3_FCLK Func 48 MMC3_GFCLK FUNC_192M_CLK DPLL_PER
192
MMC4 MMC4_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
MMC4_CLK_32K Func 0.032 L4PER_32K_GFCLK FUNC_32K_CLK OSC0
MMC4_FCLK Func 48 MMC4_GFCLK FUNC_192M_CLK DPLL_PER
192
MMU_EDMA MMU1_CLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
MMU_PCIESS MMU2_CLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
MPU MPU_CLK Int & Func MPU_CLK MPU_GCLK MPU_GCLK DPLL_MPU
MPU_EMU_DBG FCLK Int 38.4 EMU_SYS_CLK SYS_CLK1 OSC0
MPU_GCLK DPLL_MPU
OCMC_RAM1 OCMC1_L3_CLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
OCMC_ROM OCMC_L3_CLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
OCP_WP_NOC PICLKOCPL3 Int 266 L3INSTR_L3_GICLK CORE_X2_CLK DPLL_CORE
OCP2SCP1 L4CFG1_ADAPTER_CLKIN Int 133 L3INIT_L4_GICLK CORE_X2_CLK DPLL_CORE
OCP2SCP2 L4CFG2_ADAPTER_CLKIN Int 133 L4CFG_L4_GICLK CORE_X2_CLK DPLL_CORE
OCP2SCP3 L4CFG3_ADAPTER_CLKIN Int 133 L3INIT_L4_GICLK CORE_X2_CLK DPLL_CORE
PCIESS1 PCIE1_PHY_WKUP_CLK Func 0.032 PCIE_32K_GFCLK FUNC_32K_CLK DPLL_CORE
PCIe_SS1_FICLK Int 266 PCIE_L3_GICLK CORE_X2_CLK
PCIEPHY_CLK Func 2500 PCIE_PHY_GCLK PCIE_PHY_GCLK APLL_PCIE
PCIEPHY_CLK_DIV Func 1250 PCIE_PHY_DIV_GCLK PCIE_PHY_DIV_GCLK APLL_PCIE
PCIE1_REF_CLKIN Func 34.3 PCIE_REF_GFCLK CORE_USB_OTG_SS_LFPS_TX_CLK DPLL_CORE
PCIE1_PWR_CLK Func 38.4 PCIE_SYS_GFCLK SYS_CLK1 OSC0
PCIESS2 PCIE2_PHY_WKUP_CLK Func 0.032 PCIE_32K_GFCLK FUNC_32K_CLK DPLL_CORE
PCIe_SS2_FICLK Func 266 PCIE_L3_GICLK CORE_X2_CLK
PCIEPHY_CLK Func 2500 PCIE_PHY_GCLK PCIE_PHY_GCLK APLL_PCIE
PCIEPHY_CLK_DIV Func 1250 PCIE_PHY_DIV_GCLK PCIE_PHY_DIV_GCLK APLL_PCIE
PCIE2_REF_CLKIN Func 34.3 PCIE_REF_GFCLK CORE_USB_OTG_SS_LFPS_TX_CLK DPLL_CORE
PCIE2_PWR_CLK Func 38.4 PCIE_SYS_GFCLK SYS_CLK1 OSC0
PRCM_MPU 32K_CLK Func 0.032 FUNC_32K_CLK SYS_CLK1/610 OSC0
SYS_CLK Func 38.4 WKUPAON_ICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
PWMSS1 PWMSS1_GICLK Int & Func 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
PWMSS2 PWMSS2_GICLK Int & Func 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
PWMSS3 PWMSS3_GICLK Int & Func 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
QSPI QSPI_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
QSPI_FCLK Func 128 QSPI_GFCLK FUNC_256M_CLK DPLL_PER
PER_QSPI_CLK DPLL_PER
RNG RNG_ICLK Int 266 L4SEC_L3_GICLK CORE_X2_CLK DPLL_CORE
SAR_ROM PRCM_ROM_CLOCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
SDMA SDMA_FCLK Int & Func 266 DMA_L3_GICLK CORE_X2_CLK DPLL_CORE
SHA2MD51 SHAM_1_CLK Int 266 L4SEC_L3_GICLK CORE_X2_CLK DPLL_CORE
SHA2MD52 SHAM_2_CLK Int 266 L4SEC_L3_GICLK CORE_X2_CLK DPLL_CORE
SL2 IVA_GCLK Int IVA_GCLK IVA_GCLK IVA_GFCLK DPLL_IVA
SMARTREFLEX_CORE MCLK Int 133 COREAON_L4_GICLK CORE_X2_CLK DPLL_CORE
SYSCLK Func 38.4 WKUPAON_ICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
SMARTREFLEX_DSP MCLK Int 133 COREAON_L4_GICLK CORE_X2_CLK DPLL_CORE
SYSCLK Func 38.4 WKUPAON_ICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
SMARTREFLEX_GPU MCLK Int 133 COREAON_L4_GICLK CORE_X2_CLK DPLL_CORE
SYSCLK Func 38.4 WKUPAON_ICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
SMARTREFLEX_IVAHD MCLK Int 133 COREAON_L4_GICLK CORE_X2_CLK DPLL_CORE
SYSCLK Func 38.4 WKUPAON_ICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
SMARTREFLEX_MPU MCLK Int 133 COREAON_L4_GICLK CORE_X2_CLK DPLL_CORE
SYSCLK Func 38.4 WKUPAON_ICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
SPINLOCK SPINLOCK_ICLK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER1 TIMER1_ICLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
TIMER1_FCLK Func 100 TIMER1_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
TIMER2 TIMER2_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER2_FCLK Func 100 TIMER2_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
TIMER3 TIMER3_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER3_FCLK Func 100 TIMER3_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
TIMER4 TIMER4_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER4_FCLK Func 100 TIMER4_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
TIMER5 TIMER5_ICLK Int 266 IPU_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER5_FCLK Func 100 TIMER5_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
CLKOUTMUX[0] CLKOUTMUX[0]
TIMER6 TIMER6_ICLK Int 266 IPU_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER6_FCLK Func 100 TIMER6_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
CLKOUTMUX[0] CLKOUTMUX[0]
TIMER7 TIMER7_ICLK Int 266 IPU_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER7_FCLK Func 100 TIMER7_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
CLKOUTMUX[0] CLKOUTMUX[0]
TIMER8 TIMER8_ICLK Int 266 IPU_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER8_FCLK Func 100 TIMER8_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
CLKOUTMUX[0] CLKOUTMUX[0]
TIMER9 TIMER9_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER9_FCLK Func 100 TIMER9_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
TIMER10 TIMER10_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER10_FCLK Func 100 TIMER10_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
TIMER11 TIMER11_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER11_FCLK Func 100 TIMER11_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
TIMER12 TIMER12_ICLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
TIMER12_FCLK Func 0.032 OSC_32K_CLK RC_CLK RC oscillator
TIMER13 TIMER13_ICLK Int 266 L4PER3_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER13_FCLK Func 100 TIMER13_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
TIMER14 TIMER14_ICLK Int 266 L4PER3_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER14_FCLK Func 100 TIMER14_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
TIMER15 TIMER15_ICLK Int 266 L4PER3_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER15_FCLK Func 100 TIMER15_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
TIMER16 TIMER16_ICLK Int 266 L4PER3_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER16_FCLK Func 100 TIMER16_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CLK DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
TPCC TPCC_GCLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
TPTC1 TPTC0_GCLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
TPTC2 TPTC1_GCLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
UART1 UART1_FCLK Func 48 UART1_GFCLK FUNC_192M_CLK DPLL_PER
UART1_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
UART2 UART2_FCLK Func 48 UART2_GFCLK FUNC_192M_CLK
DPLL_PER
UART2_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
UART3 UART3_FCLK Func 48 UART3_GFCLK FUNC_192M_CLK DPLL_PER
UART3_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
UART4 UART4_FCLK Func 48 UART4_GFCLK FUNC_192M_CLK DPLL_PER
UART4_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
UART5 UART5_FCLK Func 48 UART5_GFCLK FUNC_192M_CLK DPLL_PER
UART5_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
UART6 UART6_FCLK Func 48 UART6_GFCLK FUNC_192M_CLK DPLL_PER
UART6_ICLK Int 266 IPU_L3_GICLK CORE_X2_CLK DPLL_CORE
UART7 UART7_FCLK Func 48 UART7_GFCLK FUNC_192M_CLK DPLL_PER
UART7_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
UART8 UART8_FCLK Func 48 UART8_GFCLK FUNC_192M_CLK DPLL_PER
UART8_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
UART9 UART9_FCLK Func 48 UART9_GFCLK FUNC_192M_CLK DPLL_PER
UART9_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE
UART10 UART10_FCLK Func 48 UART10_GFCLK FUNC_192M_CLK DPLL_PER
UART10_ICLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
USB1 USB1_MICLK Int 266 L3INIT_L3_GICLK CORE_X2_CLK DPLL_CORE
USB3PHY_REF_CLK Func 34.3 USB_LFPS_TX_GFCLK CORE_USB_OTG_SS_LFPS_TX_CLK DPLL_CORE
USB2PHY1_TREF_CLK Func 38.4 USB_OTG_SS_REF_CLK SYS_CLK1 OSC0
USB2PHY1_REF_CLK Func 960 L3INIT_960M_GFCLK L3INIT_960_GFCLK DPLL_USB
USB2 USB2_MICLK Int 266 L3INIT_L3_GICLK CORE_X2_CLK DPLL_CORE
USB2PHY2_TREF_CLK Func 38.4 USB_OTG_SS_REF_CLK SYS_CLK1 OSC0
USB2PHY2_REF_CLK Func 960 L3INIT_960M_GFCLK L3INIT_960_GFCLK DPLL_USB
USB3 USB3_MICLK Int 266 L3INIT_L3_GICLK CORE_X2_CLK DPLL_CORE
USB3PHY_PWRS_CLK Func 38.4 USB_OTG_SS_REF_CLK SYS_CLK1 OSC0
USB_PHY1_CORE USB2PHY1_WKUP_CLK Func 0.032 COREAON_32K_GFCLK SYS_CLK1/610 OSC0
USB_PHY2_CORE USB2PHY2_WKUP_CLK Func 0.032 COREAON_32K_GFCLK SYS_CLK1/610 OSC0
USB_PHY3_CORE USB3PHY_WKUP_CLK Func 0.032 COREAON_32K_GFCLK SYS_CLK1/610 OSC0
VCP1 VCP1_CLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
VCP2 VCP2_CLK Int 266 L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE
VIP1 L3_CLK_PROC_CLK Int & Func 266 VIP1_GCLK CORE_X2_CLK DPLL_CORE
CORE_ISS_MAIN_CLK DPLL_CORE
VPE L3_CLK_PROC_CLK Int & Func 300 VPE_GCLK CORE_ISS_MAIN_CLK DPLL_CORE
VIDEO1_CLKOUT4 DPLL_VIDEO1
WD_TIMER1 PIOCPCLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
PITIMERCLK Func 0.032 OSC_32K_CLK RC_CLK RC oscillator
WD_TIMER2 WD_TIMER2_ICLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CLK DPLL_ABE
WD_TIMER2_FCLK Func 0.032 WKUPAON_SYS_GFCLK WKUPAON_32K_GFCLK