JAJSFL2H March   2016  – November 2019 DRA722 , DRA724 , DRA725 , DRA726

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2 改訂履歴
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Ports (VIP)
      2. 4.4.2  Display Subsystem – Video Output Ports
      3. 4.4.3  Display Subsystem – High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  Camera Serial Interface 2 CAL bridge (CSI2)
      5. 4.4.5  External Memory Interface (EMIF)
      6. 4.4.6  General-Purpose Memory Controller (GPMC)
      7. 4.4.7  Timers
      8. 4.4.8  Inter-Integrated Circuit Interface (I2C)
      9. 4.4.9  HDQ / 1-Wire Interface (HDQ1W)
      10. 4.4.10 Universal Asynchronous Receiver Transmitter (UART)
      11. 4.4.11 Multichannel Serial Peripheral Interface (McSPI)
      12. 4.4.12 Quad Serial Peripheral Interface (QSPI)
      13. 4.4.13 Multicannel Audio Serial Port (McASP)
      14. 4.4.14 Universal Serial Bus (USB)
      15. 4.4.15 SATA
      16. 4.4.16 Peripheral Component Interconnect Express (PCIe)
      17. 4.4.17 Controller Area Network Interface (DCAN)
      18. 4.4.18 Ethernet Interface (GMAC_SW)
      19. 4.4.19 Media Local Bus (MLB) Interface
      20. 4.4.20 eMMC/SD/SDIO
      21. 4.4.21 General-Purpose Interface (GPIO)
      22. 4.4.22 Keyboard controller (KBD)
      23. 4.4.23 Pulse Width Modulation (PWM) Interface
      24. 4.4.24 Audio Tracking Logic (ATL)
      25. 4.4.25 Test Interfaces
      26. 4.4.26 System and Miscellaneous
        1. 4.4.26.1 Sysboot
        2. 4.4.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.4.26.3 Real-Time Clock (RTC) Interface
        4. 4.4.26.4 System Direct Memory Access (SDMA)
        5. 4.4.26.5 Interrupt Controllers (INTC)
        6. 4.4.26.6 Observability
      27. 4.4.27 Power Supplies
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On-Hour (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  LVCMOS CSI2 DC Electrical Characteristics
      8. 5.7.8  BMLB18 Buffers DC Electrical Characteristics
      9. 5.7.9  BC1833IHHV Buffers DC Electrical Characteristics
      10. 5.7.10 USBPHY DC Electrical Characteristics
      11. 5.7.11 Dual Voltage SDIO1833 DC Electrical Characteristics
      12. 5.7.12 Dual Voltage LVCMOS DC Electrical Characteristics
      13. 5.7.13 SATAPHY DC Electrical Characteristics
      14. 5.7.14 PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-20 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Characteristics
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Power Supply Sequences
  6. 6 Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
        3. 6.1.4.3 RC On-die Oscillator Clock
    2. 6.2 DPLLs, DLLs Specifications
      1. 6.2.1 DPLL Characteristics
      2. 6.2.2 DLL Characteristics
      3. 6.2.3 DPLL and DLL Noise Isolation
  7. 7 Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem - Video Output Ports
    8. 7.8  Display Subsystem - High-Definition Multimedia Interface (HDMI)
    9. 7.9  Camera Serial Interface 2 CAL bridge (CSI2)
      1. 7.9.1 CSI-2 MIPI D-PHY
    10. 7.10 External Memory Interface (EMIF)
    11. 7.11 General-Purpose Memory Controller (GPMC)
      1. 7.11.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.11.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.11.3 GPMC/NAND Flash Interface Asynchronous Timing
    12. 7.12 Timers
    13. 7.13 Inter-Integrated Circuit Interface (I2C)
      1. Table 7-33 Timing Requirements for I2C Input Timings
      2. Table 7-34 Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)
      3. Table 7-35 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
    14. 7.14 HDQ / 1-Wire Interface (HDQ1W)
      1. 7.14.1 HDQ / 1-Wire - HDQ Mode
      2. 7.14.2 HDQ/1-Wire-1-Wire Mode
    15. 7.15 Universal Asynchronous Receiver Transmitter (UART)
      1. Table 7-40 Timing Requirements for UART
      2. Table 7-41 Switching Characteristics Over Recommended Operating Conditions for UART
    16. 7.16 Multichannel Serial Peripheral Interface (McSPI)
    17. 7.17 Quad Serial Peripheral Interface (QSPI)
    18. 7.18 Multichannel Audio Serial Port (McASP)
      1. Table 7-48 Timing Requirements for McASP1
      2. Table 7-49 Timing Requirements for McASP2
      3. Table 7-50 Timing Requirements for McASP3/4/5/6/7/8
    19. 7.19 Universal Serial Bus (USB)
      1. 7.19.1 USB1 DRD PHY
      2. 7.19.2 USB2 PHY
      3. 7.19.3 USB3 DRD ULPI-SDR-Slave Mode-12-pin Mode
    20. 7.20 Serial Advanced Technology Attachment (SATA)
    21. 7.21 Peripheral Component Interconnect Express (PCIe)
    22. 7.22 Controller Area Network Interface (DCAN)
      1. Table 7-68 Timing Requirements for DCANx Receive
      2. Table 7-69 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
    23. 7.23 Ethernet Interface (GMAC_SW)
      1. 7.23.1 GMAC MII Timings
        1. Table 7-70 Timing Requirements for miin_rxclk - MII Operation
        2. Table 7-71 Timing Requirements for miin_txclk - MII Operation
        3. Table 7-72 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
        4. Table 7-73 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
      2. 7.23.2 GMAC MDIO Interface Timings
      3. 7.23.3 GMAC RMII Timings
        1. Table 7-78 Timing Requirements for GMAC REF_CLK - RMII Operation
        2. Table 7-79 Timing Requirements for GMAC RMIIn Receive
        3. Table 7-80 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
        4. Table 7-81 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
      4. 7.23.4 GMAC RGMII Timings
        1. Table 7-85 Timing Requirements for rgmiin_rxc - RGMIIn Operation
        2. Table 7-86 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
        3. Table 7-87 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
        4. Table 7-88 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
    24. 7.24 Media Local Bus (MLB) interface
    25. 7.25 eMMC/SD/SDIO
      1. 7.25.1 MMC1-SD Card Interface
        1. 7.25.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.25.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.25.1.3 SDR12, 4-bit data, half-cycle
        4. 7.25.1.4 SDR25, 4-bit data, half-cycle
        5. 7.25.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.25.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.25.1.7 UHS-I DDR50, 4-bit data
      2. 7.25.2 MMC2 - eMMC
        1. 7.25.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.25.2.2 High Speed JC64 SDR, 8-bit data, half cycle
        3. 7.25.2.3 High Speed HS200 JEDS84 SDR, 8-bit data, half cycle
        4. 7.25.2.4 High Speed JC64 DDR, 8-bit data
          1. Table 7-119 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
      3. 7.25.3 MMC3 and MMC4-SDIO/SD
        1. 7.25.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.25.3.2 MMC3 and MMC4, SD High Speed
        3. 7.25.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.25.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.25.3.5 MMC3 SDIO High Speed UHS-I SDR50 Mode, Half Cycle
    26. 7.26 General-Purpose Interface (GPIO)
    27. 7.27 Audio Tracking Logic (ATL)
      1. 7.27.1 ATL Electrical Data/Timing
        1. Table 7-141 Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
    28. 7.28 System and Miscellaneous interfaces
    29. 7.29 Test Interfaces
      1. 7.29.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.29.1.1 JTAG Electrical Data/Timing
          1. Table 7-142 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 7-143 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 7-144 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 7-145 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
      2. 7.29.2 Trace Port Interface Unit (TPIU)
        1. 7.29.2.1 TPIU PLL DDR Mode
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Introduction
      1. 8.1.1 Initial Requirements and Guidelines
    2. 8.2 Power Optimizations
      1. 8.2.1 Step 1: PCB Stack-up
      2. 8.2.2 Step 2: Physical Placement
      3. 8.2.3 Step 3: Static Analysis
        1. 8.2.3.1 PDN Resistance and IR Drop
      4. 8.2.4 Step 4: Frequency Analysis
      5. 8.2.5 System ESD Generic Guidelines
        1. 8.2.5.1 System ESD Generic PCB Guideline
        2. 8.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 8.2.5.3 ESD Protection System Design Consideration
      6. 8.2.6 EMI / EMC Issues Prevention
        1. 8.2.6.1 Signal Bandwidth
        2. 8.2.6.2 Signal Routing
          1. 8.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 8.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 8.2.6.3 Ground Guidelines
          1. 8.2.6.3.1 PCB Outer Layers
          2. 8.2.6.3.2 Metallic Frames
          3. 8.2.6.3.3 Connectors
          4. 8.2.6.3.4 Guard Ring on PCB Edges
          5. 8.2.6.3.5 Analog and Digital Ground
    3. 8.3 Core Power Domains
      1. 8.3.1 General Constraints and Theory
      2. 8.3.2 Voltage Decoupling
      3. 8.3.3 Static PDN Analysis
      4. 8.3.4 Dynamic PDN Analysis
      5. 8.3.5 Power Supply Mapping
      6. 8.3.6 DPLL Voltage Requirement
      7. 8.3.7 Loss of Input Power Event
      8. 8.3.8 Example PCB Design
        1. 8.3.8.1 Example Stack-up
        2. 8.3.8.2 vdd Example Analysis
    4. 8.4 Single-Ended Interfaces
      1. 8.4.1 General Routing Guidelines
      2. 8.4.2 QSPI Board Design and Layout Guidelines
    5. 8.5 Differential Interfaces
      1. 8.5.1 General Routing Guidelines
      2. 8.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 8.5.2.1 Background
        2. 8.5.2.2 USB PHY Layout Guide
          1. 8.5.2.2.1 General Routing and Placement
          2. 8.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 8.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 8.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 8.5.2.2.2.3  Board Stackup
            4. 8.5.2.2.2.4  Cable Connector Socket
            5. 8.5.2.2.2.5  Clock Routings
            6. 8.5.2.2.2.6  Crystals/Oscillator
            7. 8.5.2.2.2.7  DP/DM Trace
            8. 8.5.2.2.2.8  DP/DM Vias
            9. 8.5.2.2.2.9  Image Planes
            10. 8.5.2.2.2.10 Power Regulators
        3. 8.5.2.3 References
      3. 8.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 8.5.3.1 USB 3.0 interface introduction
        2. 8.5.3.2 USB 3.0 General routing rules
      4. 8.5.4 HDMI Board Design and Layout Guidelines
        1. 8.5.4.1 HDMI Interface Schematic
        2. 8.5.4.2 TMDS General Routing Guidelines
        3. 8.5.4.3 TPD5S115
        4. 8.5.4.4 HDMI ESD Protection Device (Required)
        5. 8.5.4.5 PCB Stackup Specifications
        6. 8.5.4.6 Grounding
      5. 8.5.5 SATA Board Design and Layout Guidelines
        1. 8.5.5.1 SATA Interface Schematic
        2. 8.5.5.2 Compatible SATA Components and Modes
        3. 8.5.5.3 PCB Stackup Specifications
        4. 8.5.5.4 Routing Specifications
      6. 8.5.6 PCIe Board Design and Layout Guidelines
        1. 8.5.6.1 PCIe Connections and Interface Compliance
          1. 8.5.6.1.1 Coupling Capacitors
          2. 8.5.6.1.2 Polarity Inversion
        2. 8.5.6.2 Non-standard PCIe connections
          1. 8.5.6.2.1 PCB Stackup Specifications
          2. 8.5.6.2.2 Routing Specifications
            1. 8.5.6.2.2.1 Impedance
            2. 8.5.6.2.2.2 Differential Coupling
            3. 8.5.6.2.2.3 Pair Length Matching
        3. 8.5.6.3 LJCB_REFN/P Connections
      7. 8.5.7 CSI2 Board Design and Routing Guidelines
        1. 8.5.7.1 CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
          1. 8.5.7.1.1 General Guidelines
          2. 8.5.7.1.2 Length Mismatch Guidelines
            1. 8.5.7.1.2.1 CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
          3. 8.5.7.1.3 Frequency-domain Specification Guidelines
    6. 8.6 Clock Routing Guidelines
      1. 8.6.1 32-kHz Oscillator Routing
      2. 8.6.2 Oscillator Ground Connection
    7. 8.7 DDR3 Board Design and Layout Guidelines
      1. 8.7.1 DDR3 General Board Layout Guidelines
      2. 8.7.2 DDR3 Board Design and Layout Guidelines
        1. 8.7.2.1  Board Designs
        2. 8.7.2.2  DDR3 EMIF
        3. 8.7.2.3  DDR3 Device Combinations
        4. 8.7.2.4  DDR3 Interface Schematic
          1. 8.7.2.4.1 32-Bit DDR3 Interface
          2. 8.7.2.4.2 16-Bit DDR3 Interface
        5. 8.7.2.5  Compatible JEDEC DDR3 Devices
        6. 8.7.2.6  PCB Stackup
        7. 8.7.2.7  Placement
        8. 8.7.2.8  DDR3 Keepout Region
        9. 8.7.2.9  Bulk Bypass Capacitors
        10. 8.7.2.10 High Speed Bypass Capacitors
          1. 8.7.2.10.1 Return Current Bypass Capacitors
        11. 8.7.2.11 Net Classes
        12. 8.7.2.12 DDR3 Signal Termination
        13. 8.7.2.13 VREF_DDR Routing
        14. 8.7.2.14 VTT
        15. 8.7.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.7.2.15.1 Four DDR3 Devices
            1. 8.7.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.7.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.7.2.15.2 Two DDR3 Devices
            1. 8.7.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.7.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.7.2.15.3 One DDR3 Device
            1. 8.7.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.7.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.7.2.16 Data Topologies and Routing Definition
          1. 8.7.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.7.2.17 Routing Specification
          1. 8.7.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.7.2.17.2 DQS and DQ Routing Specification
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Related Links
    5. 9.5 Support Resources
    6. 9.6 商標
    7. 9.7 静電気放電に関する注意事項
    8. 9.8 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ABC|760
サーマルパッド・メカニカル・データ
発注情報

8.2.3 Step 3: Static Analysis

Delivering reliable power to circuits is always of critical importance because voltage drops (also known as IR drops) can happen at every level within an electronic system, on-chip, within a package, and across the board. Robust system performance can only be ensured by understanding how the system elements will perform under typical stressful Use Cases. Therefore, it is a good practice to perform a Static or DC Analysis.

Static or DC analysis and design methodology results in a PDN design that minimizes voltage or IR drops across power and ground planes, traces and vias. This ensures the application processor’s internal transistors will be operating within their specified voltage ranges for proper functionality. The amount of IR drop that will be encounter is based upon amount power drawn for a desired Use Case and PCB trace (widths, geometry and number of parallel traces) and via (size, type and number) characteristics.

Components that are distant from their power source are particularly susceptible to IR drop. Designs that rely on battery power must minimize voltage drops to avoid unacceptable power loss that can negatively impact system performance. Early assessments a PDN’s static (DC) performance helps to determine basic power distribution parameters such as best system input power point, optimal PCB layer stackup, and copper area needed for load currents.

DRA722 DRA724 DRA725 DRA726 SPRS906_PCB_STATIC_01.gifFigure 8-3 Depiction of Sheet Resistivity and Resistance

Ohm’s Law (V = I × R) relates conduction current to voltage drop. At DC, the relation coefficient is a constant and represents the resistance of the conductor. Even current carrying conductors will dissipate power at high currents even though their resistance may be very small. Both voltage drop and power dissipation are proportional to the resistance of the conductor.

Figure 8-4 shows a PCB-level static IR drop budget defined between the power management device (PMIC) pins and the application processor’s balls when the PMIC is supplying power.

  • It is highly recommended to physically place the PMIC as close as possible to the processor and on the same side. The orientation of the PMIC vs. processor should be aligned to minimize distance for the highest current rail.
DRA722 DRA724 DRA725 DRA726 SPRS906_PCB_STATIC_01.gifFigure 8-4 Static IR Drop Budget for PCB Only

The system-level IR drop budget is made up of three portions: on-chip, package, and PCB board. Static IR or DC analysis/design methodology consists of designing the PDN such that the voltage drop (under DC operating conditions) across power and ground pads of the transistors of the application processor device is within a specified value of the nominal voltage for proper functionality of the device.

A PCB system-level voltage drop budget for proper device functionality is typically 1.5% of nominal voltage. For a 1.35-V supply, this would be ≤20 mV.

To accurately analyze PCB static IR drop, the actual geometry of the PDN must be modeled properly and simulated to accurately characterize long distribution paths, copper weight impacts, electro-migration violations of current-carrying vias, and “Swiss-cheese” effects via placement has on power rails. It is recommended to perform the following analyses:

  • Lumped resistance/IR drop analysis
  • Distributed resistance/IR drop analysis

NOTE

The PMIC companion device supporting this processor has been designed with voltage sensing feedback loop capabilities that enable a remote sense of the SMPS output voltage at the point of use.

The NOTE above means the SMPS feedback signals and returns must be routed across PCB and connected to the Device input power ball for which a particular SMPS is supplying power. This feedback loop provides compensation for some of the voltage drop encountered across the PDN within limits. As such, the effective resistance of the PDN within this loop should be determined in order to optimize voltage compensation loop performance. The resistance of two PDN segments are of interest: one from the power inductor/bulk power filtering capacitor node to the Processor’s input power and second is the entire PDN route from SMPS output pin/ball to the Processor input power.

In the following sections each methodology is described in detail and an example has been provided of analysis flow that can be used by the PCB designer to validate compliance to the requirements on their PCB PDN design.