5.10.3 Power Supply Sequences

This section describes the power-up and power-down sequence required to ensure proper device operation. The power supply names described in this section comprise a superset of a family of compatible devices. Some members of this family will not include a subset of these power supplies and their associated device modules. Refer to the Section 4.2, Pin Attributes of the Section 4, Terminal Configuration and Functions to determine which power supplies are applicable.

Figure 5-5 and Figure 5-6, describe the device power sequencing.

Figure 5-5 Recommended Power-Up Sequencing

1. Time stamps:
   • T0 = 0 ms; T1 = 0.55 ms; T2 = 1.1 ms; T3 = 1.65 ms; T4 = 2.2 ms; T5 = 2.75 ms; T6 = 3.3 ms; T7 = 5.85 ms; T8 = 6.4 ms; T9 = 8.4 ms. All “Tn” markers show total elapsed time from T0.
2. Terminology:
   • V_{OPR MIN} = Minimum Operational Voltage level that ensures device functionality and specified performance per Section 5.4, Recommended Operating Conditions.
   • Ramp Up = transition time from V_OFF to V_{OPR MIN}.
3. General timing diagram items:
   • Grey shaded areas show valid transition times for supplies between V_{OPR MIN} and V_OFF.
   • Dashed horizontal lines are not valid ramp times but show alternate transition times based upon common sources and clarified in associated note.
   • Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power sequencer circuit performance.
4. vdda_* rails should not be combined with vdds18v_* for best performance to avoid transient switching noise impacts on analog domains. vdda_* should not ramp-up before vdds18v_* but could ramp concurrently if design ensures final operational voltage will not be reached until after vdds18v. The preferred sequence is to follow all vdds18v_* to ensure circuit components and PCB design do not cause an inadvertent violation
5. vdds_ddr* should not ramp-up before vdds18v_*. The preferred sequence has vdds_ddr1 following vdds18v_* to ensure circuit components and PCB design do not cause an inadvertent violation. vdds_ddr1 can ramp-up before, concurrently or after vdda_*, there are no dependencies between vdds_ddr1 and vdda_* domains.
6. vdd should not ramp-up before vdds18v_* or vdds_ddr* domains have reached V_{OPR MIN}.
7. vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve domains should follow vdd core supply as preferred sequence. If vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve domains ramp concurrently or quicker than vdd core, then vdd core must remain at least 150 mV greater than vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve domains during ramp. Circuit design (components and PCB) must ensure vdd reaches final operational voltage before any of the vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve domains.
8. VDDA_PHY group should not be combined with VDDA_PLL group to avoid transient switching noise impacts.
9. vddshv[1-7, 9-11] domains:
   • If 1.8 V I/O signaling is needed, then 1.8 V must be sourced from common vdds18v supply and ramp up concurrently with vdds18v.
   • If 3.3 V I/O signaling is needed, then 3.3 V vddshvx rails must ramp up after vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve, and VDDA_PHY group domains.
10. vdda33v_usb[1-2] domain:
    • If USB1 and USB2 interfaces are used, should be supplied from independent analog supply.
    • If USB1/USB2 interface is not used, could be connected to VSS/GND if both conditions are met:
      • USB1/USB2 diff pair (usb1_dm/usb1_dp; usb2_dm/usb2_dp) pins are left unconnected
      • vdda_usb1 and/or vdda_usb2 PHY is not energized
11. vddshv8 shows two ramp up options for 1.8 V I/O or 3.3 V I/O or SD Card operation:
    • If 1.8 V I/O signaling is needed, then vddshv8 must ramp up after vdd and before or concurrently with 3.3 V vddshv* rails.
    • If 3.3 V I/O signaling is needed, then vddshv8 must be combined with other 3.3 V vddshv* rails.
    • If SD Card operation is needed, then vddshv8 must be sourced from a dual voltage (3.3 V / 1.8 V) power source per SDIO specifications and ramp up concurrently with 3.3 V vddshv* rails.
12. porz must remain asserted low until both of the following conditions are met:
    • Minimum of 12 × P, where P = 1 / (SYS_CLK1 / 610), units in ns.
    • All device supply rails reach stable operational levels.
13. Setup time: sysboot[15:0] pins must be valid 2P⁽¹²⁾ before porz is de-asserted high.
14. Hold time: sysboot[15:0] pins must be valid 15P⁽¹²⁾ after porz is de-asserted high.
15. rstoutn will be set high after global reset, due to porz, is de-asserted following an internal 2 ms delay. rstoutn is only valid after vddshv3 reaches an operational level. If used as a peripheral component reset, it should be AND gated with porz to avoid possible reset glitches during power up.

Figure 5-6 Recommended Power-Down Sequencing

1. Time stamps:
   • T0 = 0 ms, T1 > 100 μs, T2 = 0.5 ms, T3 = 1.0 ms, T4 = 1.5 ms; V1 = 2.7 V. All “Tn” markers are intended to show elapsed times from T0. Delta time: Δ T_D1 > 100 μs.
2. Terminology:
   • V_{OPR MIN} = Minimum Operational Voltage level that ensures device functionality and specified performance per Section 5.4, Recommended Operating Conditions table.
   • V_OFF = OFF Voltage level is defined to be less than 0.6 V where any current draw has no impact to POH.
   • Ramp Down = transition time from V_{OPR MIN} to V_OFF and is slew rate independent.
3. General timing diagram items:
   • Grey shaded areas show valid transition times for supplies between V_{OPR MIN} and V_OFF.
   • Dashed horizontal lines are not valid ramp times but show alternate transition times based upon common sources and clarified in associated note.
   • Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit performance.
4. porz signals must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.
5. vddshv* domains supplied by 3.3 V:
   • must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 µs min after porz is asserted low.
   • must be in first group of supplies ramping down after porz has been asserted low for 100 µs min.
   • must not exceed vdds18v by more than 2 V during ramp down, see Figure 5-9 “vdds18v and vdda_* Discharge Relationship”.
6. vddshv* domains supplied by 1.8 V:
   • must ramp down concurrently with vdds18v and be sourced from the same vdds18v supply.
7. vddshv8 domain:
   • must be in first group of supplies to ramp down after porz has been asserted low for 100 µs min.
   • if SDIO operation is needed, must be sourced from independent power resource that can provide dual voltage (3.3 V / 1.8 V) operation as required to be compliant to SDIO specification
   • if SDIO operation is not needed, must be grouped and ramped down with other vddshv* domains as noted above.
8. vdda_* domains:
   • should not be combined with vdds18v for best performance to avoid transient switching noise impacts on analog domains.
   • can ramp down before or concurrently with vdds18v.
   • must satisfy the vdds18v and vdda_* Discharge Relationship (see Figure 5-9) if vdda_* disable point is later or discharge rate is slower than vdds18v.
   • can ramp down before, concurrently or after vdds_ddr*, there is no dependency between these supplies.
9. vdda33v_usb* domains:
   • can start ramping down 100 µs after low assertion of porz
   • can ramp down concurrently or before VDDA_PHY group
10. vdd_dspeve, vdd_gpu, vdd_iva, vdd_mpu domains can ramp down before or concurrently with vdd.
11. vdd can ramp down concurrently or after with vdd_dspeve, vdd_gpu, vdd_iva, vdd_mpu domains.
12. vdds_ddr* domains:
    • should ramp down after vdd begins ramping down.
13. vdds18v domain:
    • should maintain V_{OPR MIN} (V_NOM -5% = 1.71 V) until all other supplies start to ramp down.
    • must satisfy the vdds18v versus vddshv[1-7, 9-11] Discharge Relationship (see Figure 5-7) if vddshv* is operating at 3.3 V
    • must satisfy the vdds18v and vdds_ddr* Discharge Relationship (see Figure 5-8) if vdds_ddr* discharge rate is slower than vdds18v.

Figure 5-7 describes vddshv[1-7,9-11] supplies falling before vdds18v supplies delta.

Figure 5-7 vdds18v versus vddshv[1-7, 9-11] Discharge Relationship

1. Vdelta MAX = 2 V.
2. If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails.

If vdds18v and vdds_ddr* are disabled at the same time due to a loss of input power event or if vdds_ddr* discharges more slowly than vdds18v, analysis has shown no reliability impacts when the elapsed time period beginning with vdds18v dropping below 1.0 V and ending with vdds_ddr* dropping below 0.6 V is less than 10 ms (Figure 5-8).

Figure 5-8 vdds18v and vdds_ddr* Discharge Relationship⁽¹⁾

1. V1 > 1.0 V; V2 < 0.6 V; T1 < 10 ms.

Figure 5-9 vdds18v and vdda_* Discharge Relationship⁽³⁾

1. vdda_* can be ≥ vdds18v, until vdds18v drops below 1.62 V.
2. vdds18v must be ≥ vdda_*, until vdds18v reaches 0.6 V.
3. V1 = 1.62 V; V2 < 0.6 V.

Figure 5-7 through Figure 5-10 and associated notes described the device abrupt power down sequence.

A ”loss of input power event” occurs when the system’s input power is unexpectedly removed. Normally, the recommended power-down sequence should be followed and can be accomplished within 1.5-2 ms of elapsed time. This is the typical range of elapsed time available following a loss of power event, see Section 7.3.7 for design recommendations. If sufficient elapse time is not provided, then an “abrupt” power down sequence can be supported without impacting POH reliability if all of the following conditions are met (Figure 5-10).

Figure 5-10 Abrupt Power-Down Sequencing⁽¹⁾

1. Time stamps:
   • V1 = 2.7 V; V2 = 3.3 V; V3 = 2.0 V; V4 = V5 = V6 = 0.6 V; V7 = V8 = 1.62 V; V9 = 1.3 V; V10 = 1.0 V; V11 = 0.0 V; T_delta1 > 100 µs; T_delta2 < 10 ms.
2. Terminology:
   • V_{OPR MIN} = Minimum Operational Voltage level that ensures device functionality and specified performance in Section 5.4, Recommended Operating Conditions table.
   • V_OFF = OFF Voltage level is defined to be less than 0.6 V, where any current draw has no impact to POH.
   • Ramp Down = transition time from V_{OPR MIN} to V_OFF and is slew rate independent.
3. General timing diagram items:
   • Grey shaded areas show valid transition times for supplies between V_{OPR MIN} and V_OFF.
   • Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit performance.
4. porz must be asserted low for 100 μs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.
5. vddshv[1-7, 9-11] domains supplied by 3.3 V:
   • must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 μs min, after porz is asserted low.
   • must not exceed vdds18v voltage level by more than 2 V during ramp down, until vdds18v drops below V_OFF (0.6 V).
6. vddshv[1-7, 9-11] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v supply.
7. vddshv8 supporting SD Card:
   • must be in first group of supplies to ramp down after porz has been asserted low for 100 µs min.
   • must be sourced from independent power resource that can provide dual voltage (3.3 V / 1.8 V) operation as required to be compliant to SDIO specification.
   • if SDIO operation is not needed, must be grouped with other vddshv[1-7, 9-11] domains.
8. vdda33v_usb[1-2] domains must be in first group of supplies to ramp down after porz has been asserted low for 100 µs min.
9. vdd_dspeve, vdd_gpu, vdd_iva, vdd_mpu, vdd, vdds_ddr1, vdda_* domains can all start to ramp down in any order after 100 µs low assertion of porz.
10. vdds_ddr1 domains:
    • can remain at V_{OPR MIN} or a level greater than vdds18v during ramp down.
    • elapsed time from vdds18v dropping below 1.0 V to vdds_ddr[1-3] dropping below 0.6 V must not exceed 10 ms.
11. vdda_* domains:
    • can start to ramp down before or concurrently with vdds18v.
    • must not exceed vdds18v voltage level after vdds18v drops below 1.62 V until vdds18v drops below V_OFF (0.6 V).
12. vdds18v domain should maintain a minimum level of 1.62 V (V_NOM – 10%) until vdd_dspeve and vdd start to ramp down.