JAJSFR8E August   2016  – May 2019 DRA790 , DRA791 , DRA793 , DRA797

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  CSI2
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  HDQ1W
      10. 4.3.10 UART
      11. 4.3.11 McSPI
      12. 4.3.12 QSPI
      13. 4.3.13 McASP
      14. 4.3.14 USB
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 ATL
      25. 4.3.25 Emulation and Debug Subsystem
      26. 4.3.26 System and Miscellaneous
        1. 4.3.26.1 Sysboot
        2. 4.3.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.3.26.3 System Direct Memory Access (SDMA)
        4. 4.3.26.4 Interrupt Controllers (INTC)
      27. 4.3.27 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power on Hour (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS CSI2 DC Electrical Characteristics
      6. Table 5-11 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-12 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-13 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      USBPHY DC Electrical Characteristics
      10. 5.7.2      HDMIPHY DC Electrical Characteristics
      11. 5.7.3      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-14 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics for CBD Package
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.10.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RC On-die Oscillator Clock
        2. 5.10.4.2 Output Clocks
        3. 5.10.4.3 DPLLs, DLLs
          1. 5.10.4.3.1 DPLL Characteristics
          2. 5.10.4.3.2 DLL Characteristics
          3. 5.10.4.3.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  CSI2
          1. 5.10.6.6.1 CSI-2 MIPI D-PHY
        7. 5.10.6.7  EMIF
        8. 5.10.6.8  GPMC
          1. 5.10.6.8.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.8.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
        9. 5.10.6.9  Timers
        10. 5.10.6.10 I2C
          1. Table 5-56 Timing Requirements for I2C Input Timings
          2. Table 5-57 Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)
          3. Table 5-58 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        11. 5.10.6.11 HDQ1W
          1. 5.10.6.11.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.11.2 HDQ/1-Wire—1-Wire Mode
        12. 5.10.6.12 UART
          1. Table 5-63 Timing Requirements for UART
          2. Table 5-64 Switching Characteristics Over Recommended Operating Conditions for UART
        13. 5.10.6.13 McSPI
        14. 5.10.6.14 QSPI
        15. 5.10.6.15 McASP
          1. Table 5-71 Timing Requirements for McASP1
          2. Table 5-72 Timing Requirements for McASP2
          3. Table 5-73 Timing Requirements for McASP3/4/5/6/7/8
        16. 5.10.6.16 USB
          1. 5.10.6.16.1 USB1 DRD PHY
          2. 5.10.6.16.2 USB2 PHY
          3. 5.10.6.16.3 USB3 DRD ULPI—SDR—Slave Mode—12-pin Mode
        17. 5.10.6.17 PCIe
        18. 5.10.6.18 DCAN
          1. Table 5-91 Timing Requirements for DCANx Receive
          2. Table 5-92 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-93 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-94 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-95 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-96 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-101 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-102 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-103 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-104 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-108 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-109 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-111 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 MLB
        21. 5.10.6.21 eMMC/SD/SDIO
          1. 5.10.6.21.1 MMC1—SD Card Interface
            1. 5.10.6.21.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.21.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.21.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.21.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.21.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.21.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.21.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.21.2 MMC2 — eMMC
            1. 5.10.6.21.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.21.2.2 High-speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.21.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
            4. 5.10.6.21.2.4 High-speed JC64 DDR, 8-bit data
              1. Table 5-142 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
          3. 5.10.6.21.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.21.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.21.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.21.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.21.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.21.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        22. 5.10.6.22 GPIO
        23. 5.10.6.23 PRU-ICSS
          1. 5.10.6.23.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.23.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-164 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-165 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.23.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-166 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.23.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-167 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-168 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.23.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-169 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-170 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-171 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.23.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.23.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-172 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-173 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-174 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-175 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-176 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.23.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.23.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-177 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-178 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-179 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.23.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-180 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-181 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-182 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-183 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.23.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-184 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-185 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.23.5 PRU-ICSS IOSETs
          6. 5.10.6.23.6 PRU-ICSS Manual Functional Mapping
        24. 5.10.6.24 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-202 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-203 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-204 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-205 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 Trace Port Interface Unit (TPIU)
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  IPU
    6. 6.6  PRU-ICSS
    7. 6.7  Memory Subsystem
      1. 6.7.1 EMIF
      2. 6.7.2 GPMC
      3. 6.7.3 ELM
      4. 6.7.4 OCMC
    8. 6.8  Interprocessor Communication
      1. 6.8.1 MailBox
      2. 6.8.2 Spinlock
    9. 6.9  Interrupt Controller
    10. 6.10 EDMA
    11. 6.11 Peripherals
      1. 6.11.1  VIP
      2. 6.11.2  DSS
      3. 6.11.3  Timers
        1. 6.11.3.1 General-Purpose Timers
        2. 6.11.3.2 32-kHz Synchronized Timer (COUNTER_32K)
        3. 6.11.3.3 Watchdog Timer
      4. 6.11.4  I2C
      5. 6.11.5  UART
        1. 6.11.5.1 UART Features
        2. 6.11.5.2 IrDA Features
        3. 6.11.5.3 CIR Features
      6. 6.11.6  McSPI
      7. 6.11.7  QSPI
      8. 6.11.8  McASP
      9. 6.11.9  USB
      10. 6.11.10 PCIe
      11. 6.11.11 DCAN
      12. 6.11.12 GMAC_SW
      13. 6.11.13 eMMC/SD/SDIO
      14. 6.11.14 GPIO
      15. 6.11.15 ePWM
      16. 6.11.16 eCAP
      17. 6.11.17 eQEP
    12. 6.12 On-chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 Power Regulators
        3. 7.5.2.3 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 PCIe Board Design and Layout Guidelines
        1. 7.5.5.1 PCIe Connections and Interface Compliance
          1. 7.5.5.1.1 Coupling Capacitors
          2. 7.5.5.1.2 Polarity Inversion
        2. 7.5.5.2 Non-standard PCIe connections
          1. 7.5.5.2.1 PCB Stackup Specifications
          2. 7.5.5.2.2 Routing Specifications
            1. 7.5.5.2.2.1 Impedance
            2. 7.5.5.2.2.2 Differential Coupling
            3. 7.5.5.2.2.3 Pair Length Matching
        3. 7.5.5.3 LJCB_REFN/P Connections
      6. 7.5.6 CSI2 Board Design and Routing Guidelines
        1. 7.5.6.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.6.1.1 General Guidelines
          2. 7.5.6.1.2 Length Mismatch Guidelines
            1. 7.5.6.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.6.1.3 Frequency-domain Specification Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7 DDR3 Board Design and Layout Guidelines
      1. 7.7.1 DDR3 General Board Layout Guidelines
      2. 7.7.2 DDR3 Board Design and Layout Guidelines
        1. 7.7.2.1  Board Designs
        2. 7.7.2.2  DDR3 EMIF
        3. 7.7.2.3  DDR3 Device Combinations
        4. 7.7.2.4  DDR3 Interface Schematic
          1. 7.7.2.4.1 32-Bit DDR3 Interface
          2. 7.7.2.4.2 16-Bit DDR3 Interface
        5. 7.7.2.5  Compatible JEDEC DDR3 Devices
        6. 7.7.2.6  PCB Stackup
        7. 7.7.2.7  Placement
        8. 7.7.2.8  DDR3 Keepout Region
        9. 7.7.2.9  Bulk Bypass Capacitors
        10. 7.7.2.10 High-Speed Bypass Capacitors
          1. 7.7.2.10.1 Return Current Bypass Capacitors
        11. 7.7.2.11 Net Classes
        12. 7.7.2.12 DDR3 Signal Termination
        13. 7.7.2.13 VREF_DDR Routing
        14. 7.7.2.14 VTT
        15. 7.7.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.7.2.15.1 Four DDR3 Devices
            1. 7.7.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.7.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.7.2.15.2 Two DDR3 Devices
            1. 7.7.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.7.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.7.2.15.3 One DDR3 Device
            1. 7.7.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.7.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.7.2.16 Data Topologies and Routing Definition
          1. 7.7.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.7.2.17 Routing Specification
          1. 7.7.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.7.2.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • CBD|538
サーマルパッド・メカニカル・データ
発注情報

5.10.6.3 VIP

The Device includes 1 Video Input Port (VIP).

Table 5-30, Figure 5-20 and Figure 5-21 present timings and switching characteristics of the VIP.

CAUTION

The I/O timings provided in this section are valid only for VIN1 and VIN2 if signals within a single IOSET are used. The IOSETs are defined in Table 5-31.

Table 5-30 Timing Requirements for VIP (3)(4)(5)

NO. PARAMETER DESCRIPTION MIN MAX UNIT
V1 tc(CLK) Cycle time, vinx_clki (3)(5) 6.06 (2) ns
V2 tw(CLKH) Pulse duration, vinx_clki high (3)(5) 0.45 × P (2) ns
V3 tw(CLKL) Pulse duration, vinx_clki low (3)(5) 0.45 × P (2) ns
V4 tsu(CTL/DATA-CLK) Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition (3)(4)(5) 3.11 (2) ns
V6 th(CLK-CTL/DATA) Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci) and Data (vinx_dn) valid from vinx_clki transition (3)(4)(5) -0.05 (2) ns
  1. For maximum frequency of 165 MHz.
  2. P = vinx_clki period.
  3. x in vinx = 1a, 1b, 2a, 2b.
  4. n in dn = 0 to 7 when x = 1b, 2b.
    n = 0 to 23 when x = 1a, 2a.
  5. i in clki, dei, vsynci, hsynci and fldi = 0 or 1.
DRA790 DRA791 DRA793 DRA797 SPRS906_TIMING_VIP_01.gifFigure 5-20 Video Input Ports Clock Signal
DRA790 DRA791 DRA793 DRA797 SPRS906_TIMING_VIP_02.gifFigure 5-21 Video Input Ports Timings

In Table 5-31 and Table 5-32 are presented the specific groupings of signals (IOSET) for use with vin1 and vin2.

Table 5-31 VIN1 IOSETs

SIGNALS IOSET2 IOSET6(1) IOSET7(1) IOSET8 IOSET9 IOSET10
BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX
vin1a
vin1a_clk0 G3 2 Y5 9 J24 7 J24 7
vin1a_hsync0 K4 2 AA4 9 B14 7 B14 7
vin1a_vsync0 H1 2 AB1 9 D14 7 D14 7
vin1a_fld0 L3 2 C16 7 C16 7
vin1a_de0 J2 2 Y6 9 C17 7 C17 7
vin1a_d0 F1 2 AA1 9 J25 7 B23 7
vin1a_d1 E2 2 Y3 9 B22 7 B22 7
vin1a_d2 E1 2 W2 9 A23 7 A23 7
vin1a_d3 C1 2 AA3 9 A22 7 A22 7
vin1a_d4 D1 2 AA2 9 B21 7 B21 7
vin1a_d5 D2 2 Y4 9 A21 7 A21 7
vin1a_d6 B1 2 Y1 9 D19 7 D19 7
vin1a_d7 B2 2 Y2 9 E19 7 E19 7
vin1a_d8 C2 2 F16 7 F16 7
vin1a_d9 D3 2 E16 7 E16 7
vin1a_d10 A2 2 E17 7 E17 7
vin1a_d11 B3 2 A19 7 A19 7
vin1a_d12 C3 2 B18 7 B18 7
vin1a_d13 C4 2 B16 7 B16 7
vin1a_d14 A3 2 B17 7 B17 7
vin1a_d15 B4 2 A18 7 A18 7
vin1a_d16 M1 2
vin1a_d17 M2 2
vin1a_d18 L2 2
vin1a_d19 L1 2
vin1a_d20 K3 2
vin1a_d21 K2 2
vin1a_d22 J1 2
vin1a_d23 K1 2
vin1b
vin1b_clk1 L5 5 J2 6
vin1b_hsync1 P3 5 K4 6
vin1b_vsync1 R2 5 H1 6
vin1b_fld1 N4 5 G1 6
vin1b_de1 P4 5 L3 6
vin1b_d0 L6 5 M1 6
vin1b_d1 N5 5 M2 6
vin1b_d2 N6 5 L2 6
vin1b_d3 T4 5 L1 6
vin1b_d4 T5 5 K3 6
vin1b_d5 N2 5 K2 6
vin1b_d6 P2 5 J1 6
vin1b_d7 N1 5 K1 6
  1. The IOSET under this column is only applicable for pins with alternate functionality which allows either VIN1 or VIN2 signals to be mapped to the pins. These alternate functions are controlled via CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.

Table 5-32 VIN2 IOSETs

SIGNALS IOSET1 IOSET2 IOSET4 IOSET5 IOSET6 IOSET7(1) IOSET8(1) IOSET9(1)
BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX
vin2a
vin2a_clk0 D8 0 D8 0 L5 4
vin2a_hsync0 E8 0 E8 0 P3 4
vin2a_vsync0 B8 0 B8 0 R2 4
vin2a_fld0 C7 0 B7 1 N4 4
vin2a_de0 B7 0 P4 4
vin2a_d0 C8 0 C8 0 L6 4
vin2a_d1 B9 0 B9 0 N5 4
vin2a_d2 A7 0 A7 0 N6 4
vin2a_d3 A9 0 A9 0 T4 4
vin2a_d4 A8 0 A8 0 T5 4
vin2a_d5 A11 0 A11 0 N2 4
vin2a_d6 F10 0 F10 0 P2 4
vin2a_d7 A10 0 A10 0 N1 4
vin2a_d8 B10 0 B10 0 P1 4
vin2a_d9 E10 0 E10 0 N3 4
vin2a_d10 D10 0 D10 0 R1 4
vin2a_d11 C10 0 C10 0 P5 4
vin2a_d12 B11 0 B11 0
vin2a_d13 D11 0 D11 0
vin2a_d14 C11 0 C11 0
vin2a_d15 B12 0 B12 0
vin2a_d16 A12 0 A12 0
vin2a_d17 A13 0 A13 0
vin2a_d18 E11 0 E11 0
vin2a_d19 F11 0 F11 0
vin2a_d20 B13 0 B13 0
vin2a_d21 E13 0 E13 0
vin2a_d22 C13 0 C13 0
vin2a_d23 D13 0 D13 0
vin2b
vin2b_clk1 L4 6 H6 4 C7 2 C7 2 AB1 4
vin2b_hsync1 B6 6 B6 6 E8 3 E8 3 Y5 4
vin2b_vsync1 A6 6 A6 6 B8 3 B8 3 Y6 4
vin2b_fld1 H6 6 B7 2
vin2b_de1 H2 6 H2 6 B7 3 AA4 4
vin2b_d0 A4 6 A4 6 D13 2 D13 2 AA1 4
vin2b_d1 E7 6 E7 6 C13 2 C13 2 Y3 4
vin2b_d2 D6 6 D6 6 E13 2 E13 2 W2 4
vin2b_d3 C5 6 C5 6 B13 2 B13 2 AA3 4
vin2b_d4 B5 6 B5 6 F11 2 F11 2 AA2 4
vin2b_d5 D7 6 D7 6 E11 2 E11 2 Y4 4
vin2b_d6 C6 6 C6 6 A13 2 A13 2 Y1 4
vin2b_d7 A5 6 A5 6 A12 2 A12 2 Y2 4
  1. The IOSET under this column is only applicable for pins with alternate functionality which allows either VIN1 or VIN2 signals to be mapped to the pins. These alternate functions are controlled via CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.

NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information please see the Control Module Chapter in the Device TRM.

Manual IO Timings Modes must be used to ensure some IO timings for VIP1. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-33Manual Functions Mapping for VIN2A (IOSET4/5/6) for a definition of the Manual modes.

Table 5-33 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-33 Manual Functions Mapping for VIN2A (IOSET4/5/6)

BALL BALL NAME VIP_MANUAL3 VIP_MANUAL5 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 0 1 4
P5 RMII_MHZ_50_CLK 2616 1379 2798 1294 CFG_RMII_MHZ_50_CLK_IN - - vin2a_d11
L6 mdio_d 2558 1105 2790 954 CFG_MDIO_D_IN - - vin2a_d0
L5 mdio_mclk 998 463 1029 431 CFG_MDIO_MCLK_IN - - vin2a_clk0
N2 rgmii0_rxc 2658 862 2896 651 CFG_RGMII0_RXC_IN - - vin2a_d5
P2 rgmii0_rxctl 2658 1628 2844 1518 CFG_RGMII0_RXCTL_IN - - vin2a_d6
N4 rgmii0_rxd0 2638 1123 2856 888 CFG_RGMII0_RXD0_IN - - vin2a_fld0
N3 rgmii0_rxd1 2641 1737 2804 1702 CFG_RGMII0_RXD1_IN - - vin2a_d9
P1 rgmii0_rxd2 2641 1676 2801 1652 CFG_RGMII0_RXD2_IN - - vin2a_d8
N1 rgmii0_rxd3 2644 1828 2807 1790 CFG_RGMII0_RXD3_IN - - vin2a_d7
T4 rgmii0_txc 2638 1454 2835 1396 CFG_RGMII0_TXC_IN - - vin2a_d3
T5 rgmii0_txctl 2672 1663 2831 1640 CFG_RGMII0_TXCTL_IN - - vin2a_d4
R1 rgmii0_txd0 2604 1442 2764 1417 CFG_RGMII0_TXD0_IN - - vin2a_d10
R2 rgmii0_txd1 2683 1598 2843 1600 CFG_RGMII0_TXD1_IN - - vin2a_vsync0
P3 rgmii0_txd2 2563 1483 2816 1344 CFG_RGMII0_TXD2_IN - - vin2a_hsync0
P4 rgmii0_txd3 2717 1461 2913 1310 CFG_RGMII0_TXD3_IN - - vin2a_de0
N5 uart3_rxd 2445 1145 2743 923 CFG_UART3_RXD_IN - - vin2a_d1
N6 uart3_txd 2650 1197 2842 1080 CFG_UART3_TXD_IN - - vin2a_d2
D8 vin2a_clk0 0 0 0 0 CFG_VIN2A_CLK0_IN vin2a_clk0 - -
C8 vin2a_d0 1812 102 1936 0 CFG_VIN2A_D0_IN vin2a_d0 - -
B9 vin2a_d1 1701 439 2229 10 CFG_VIN2A_D1_IN vin2a_d1 - -
D10 vin2a_d10 1720 215 2031 0 CFG_VIN2A_D10_IN vin2a_d10 - -
C10 vin2a_d11 1622 0 1702 0 CFG_VIN2A_D11_IN vin2a_d11 - -
B11 vin2a_d12 1350 412 1819 0 CFG_VIN2A_D12_IN vin2a_d12 - -
D11 vin2a_d13 1613 147 1476 260 CFG_VIN2A_D13_IN vin2a_d13 - -
C11 vin2a_d14 1149 516 1701 0 CFG_VIN2A_D14_IN vin2a_d14 - -
B12 vin2a_d15 1530 450 2021 0 CFG_VIN2A_D15_IN vin2a_d15 - -
A12 vin2a_d16 1512 449 2044 11 CFG_VIN2A_D16_IN vin2a_d16 - -
A13 vin2a_d17 1293 488 1839 5 CFG_VIN2A_D17_IN vin2a_d17 - -
E11 vin2a_d18 2140 371 2494 0 CFG_VIN2A_D18_IN vin2a_d18 - -
F11 vin2a_d19 2041 275 1699 611 CFG_VIN2A_D19_IN vin2a_d19 - -
A7 vin2a_d2 1675 35 1736 0 CFG_VIN2A_D2_IN vin2a_d2 - -
B13 vin2a_d20 1972 441 2412 88 CFG_VIN2A_D20_IN vin2a_d20 - -
E13 vin2a_d21 1957 556 2391 161 CFG_VIN2A_D21_IN vin2a_d21 - -
C13 vin2a_d22 2011 433 2446 102 CFG_VIN2A_D22_IN vin2a_d22 - -
D13 vin2a_d23 1962 523 2395 145 CFG_VIN2A_D23_IN vin2a_d23 - -
A9 vin2a_d3 1457 361 1943 0 CFG_VIN2A_D3_IN vin2a_d3 - -
A8 vin2a_d4 1535 0 1601 0 CFG_VIN2A_D4_IN vin2a_d4 - -
A11 vin2a_d5 1676 271 2052 0 CFG_VIN2A_D5_IN vin2a_d5 - -
F10 vin2a_d6 1513 0 1571 0 CFG_VIN2A_D6_IN vin2a_d6 - -
A10 vin2a_d7 1616 141 1855 0 CFG_VIN2A_D7_IN vin2a_d7 - -
B10 vin2a_d8 1286 437 1224 618 CFG_VIN2A_D8_IN vin2a_d8 - -
E10 vin2a_d9 1544 265 1373 509 CFG_VIN2A_D9_IN vin2a_d9 - -
B7 vin2a_de0 1732 208 1949 0 CFG_VIN2A_DE0_IN vin2a_de0 vin2a_fld0 -
C7 vin2a_fld0 1461 562 1983 151 CFG_VIN2A_FLD0_IN vin2a_fld0 - -
E8 vin2a_hsync0 1877 0 1943 0 CFG_VIN2A_HSYNC0_IN vin2a_hsync0 - -
B8 vin2a_vsync0 1566 0 1612 0 CFG_VIN2A_VSYNC0_IN vin2a_vsync0 - -

Manual IO Timings Modes must be used to ensure some IO timings for VIP1. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-34Manual Functions Mapping for VIN2B (IOSET7/8/9) for a definition of the Manual modes.

Table 5-34 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-34 Manual Functions Mapping for VIN2B (IOSET7/8/9)

BALL BALL NAME VIP_MANUAL4 VIP_MANUAL6 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 2 3 4
Y5 gpio6_10 2829 884 3009 892 CFG_GPIO6_10_IN - - vin2b_hsync1
Y6 gpio6_11 2648 1033 2890 1096 CFG_GPIO6_11_IN - - vin2b_vsync1
Y2 mmc3_clk 2794 1074 2997 1089 CFG_MMC3_CLK_IN - - vin2b_d7
Y1 mmc3_cmd 2789 1162 2959 1210 CFG_MMC3_CMD_IN - - vin2b_d6
Y4 mmc3_dat0 2689 1180 2897 1269 CFG_MMC3_DAT0_IN - - vin2b_d5
AA2 mmc3_dat1 2605 1219 2891 1219 CFG_MMC3_DAT1_IN - - vin2b_d4
AA3 mmc3_dat2 2616 703 2947 590 CFG_MMC3_DAT2_IN - - vin2b_d3
W2 mmc3_dat3 2760 1235 2931 1342 CFG_MMC3_DAT3_IN - - vin2b_d2
Y3 mmc3_dat4 2757 880 2979 891 CFG_MMC3_DAT4_IN - - vin2b_d1
AA1 mmc3_dat5 2688 1177 2894 1262 CFG_MMC3_DAT5_IN - - vin2b_d0
AA4 mmc3_dat6 2638 1165 2894 1187 CFG_MMC3_DAT6_IN - - vin2b_de1
AB1 mmc3_dat7 995 182 1202 107 CFG_MMC3_DAT7_IN - - vin2b_clk1
A12 vin2a_d16 1423 0 1739 0 CFG_VIN2A_D16_IN vin2b_d7 - -
A13 vin2a_d17 1253 0 1568 0 CFG_VIN2A_D17_IN vin2b_d6 - -
E11 vin2a_d18 2080 0 2217 0 CFG_VIN2A_D18_IN vin2b_d5 - -
F11 vin2a_d19 1849 0 2029 0 CFG_VIN2A_D19_IN vin2b_d4 - -
B13 vin2a_d20 1881 50 2202 0 CFG_VIN2A_D20_IN vin2b_d3 - -
E13 vin2a_d21 1917 167 2313 0 CFG_VIN2A_D21_IN vin2b_d2 - -
C13 vin2a_d22 1955 79 2334 0 CFG_VIN2A_D22_IN vin2b_d1 - -
D13 vin2a_d23 1899 145 2288 0 CFG_VIN2A_D23_IN vin2b_d0 - -
B7 vin2a_de0 1568 261 2048 0 CFG_VIN2A_DE0_IN vin2b_fld1 vin2b_de1 -
C7 vin2a_fld0 0 0 0 0 CFG_VIN2A_FLD0_IN vin2b_clk1 - -
E8 vin2a_hsync0 1793 0 2011 0 CFG_VIN2A_HSYNC0_IN - vin2b_hsync1 -
B8 vin2a_vsync0 1382 0 1632 0 CFG_VIN2A_VSYNC0_IN - vin2b_vsync1 -

Manual IO Timings Modes must be used to ensure some IO timings for VIP1. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-35Manual Functions Mapping for VIN1A (IOSET2) and VIN2B (IOSET1/10) for a definition of the Manual modes.

Table 5-35 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-35 Manual Functions Mapping for VIN1A (IOSET2) and VIN2B (IOSET1/10)

BALL BALL NAME VIP_MANUAL7 VIP_MANUAL12 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 2 6
M1 gpmc_a0 3080 1792 3376 1632 CFG_GPMC_A0_IN vin1a_d16 -
M2 gpmc_a1 2958 1890 3249 1749 CFG_GPMC_A1_IN vin1a_d17 -
J2 gpmc_a10 3073 1653 3388 1433 CFG_GPMC_A10_IN vin1a_de0 -
L3 gpmc_a11 3014 1784 3290 1693 CFG_GPMC_A11_IN vin1a_fld0 -
A4 gpmc_a19 1385 0 1246 0 CFG_GPMC_A19_IN - vin2b_d0
L2 gpmc_a2 3041 1960 3322 1850 CFG_GPMC_A2_IN vin1a_d18 -
E7 gpmc_a20 859 0 720 0 CFG_GPMC_A20_IN - vin2b_d1
D6 gpmc_a21 1465 0 1334 0 CFG_GPMC_A21_IN - vin2b_d2
C5 gpmc_a22 1210 0 1064 0 CFG_GPMC_A22_IN - vin2b_d3
B5 gpmc_a23 1111 0 954 0 CFG_GPMC_A23_IN - vin2b_d4
D7 gpmc_a24 1137 0 1051 0 CFG_GPMC_A24_IN - vin2b_d5
C6 gpmc_a25 1402 0 1283 0 CFG_GPMC_A25_IN - vin2b_d6
A5 gpmc_a26 1298 0 1153 0 CFG_GPMC_A26_IN - vin2b_d7
B6 gpmc_a27 934 0 870 0 CFG_GPMC_A27_IN - vin2b_hsync1
L1 gpmc_a3 3019 2145 3296 2050 CFG_GPMC_A3_IN vin1a_d19 -
K3 gpmc_a4 3063 1981 3357 1829 CFG_GPMC_A4_IN vin1a_d20 -
K2 gpmc_a5 3021 1954 3304 1840 CFG_GPMC_A5_IN vin1a_d21 -
J1 gpmc_a6 3062 1716 3348 1592 CFG_GPMC_A6_IN vin1a_d22 -
K1 gpmc_a7 3260 1889 3583 1631 CFG_GPMC_A7_IN vin1a_d23 -
K4 gpmc_a8 3033 1702 3328 1547 CFG_GPMC_A8_IN vin1a_hsync0 -
H1 gpmc_a9 2991 1905 3281 1766 CFG_GPMC_A9_IN vin1a_vsync0 -
F1 gpmc_ad0 2907 1342 3181 1255 CFG_GPMC_AD0_IN vin1a_d0 -
E2 gpmc_ad1 2858 1321 3132 1234 CFG_GPMC_AD1_IN vin1a_d1 -
A2 gpmc_ad10 2920 1384 3223 1204 CFG_GPMC_AD10_IN vin1a_d10 -
B3 gpmc_ad11 2719 1310 3019 1198 CFG_GPMC_AD11_IN vin1a_d11 -
C3 gpmc_ad12 2845 1135 3160 917 CFG_GPMC_AD12_IN vin1a_d12 -
C4 gpmc_ad13 2765 1225 3045 1119 CFG_GPMC_AD13_IN vin1a_d13 -
A3 gpmc_ad14 2845 1150 3153 952 CFG_GPMC_AD14_IN vin1a_d14 -
B4 gpmc_ad15 2766 1453 3044 1355 CFG_GPMC_AD15_IN vin1a_d15 -
E1 gpmc_ad2 2951 1296 3226 1209 CFG_GPMC_AD2_IN vin1a_d2 -
C1 gpmc_ad3 2825 1154 3121 997 CFG_GPMC_AD3_IN vin1a_d3 -
D1 gpmc_ad4 2927 1245 3246 1014 CFG_GPMC_AD4_IN vin1a_d4 -
D2 gpmc_ad5 2923 1251 3217 1098 CFG_GPMC_AD5_IN vin1a_d5 -
B1 gpmc_ad6 2958 1342 3238 1239 CFG_GPMC_AD6_IN vin1a_d6 -
B2 gpmc_ad7 2900 1244 3174 1157 CFG_GPMC_AD7_IN vin1a_d7 -
C2 gpmc_ad8 2845 1585 3125 1482 CFG_GPMC_AD8_IN vin1a_d8 -
D3 gpmc_ad9 2779 1343 3086 1223 CFG_GPMC_AD9_IN vin1a_d9 -
H2 gpmc_ben0 1555 0 1425 0 CFG_GPMC_BEN0_IN - vin2b_de1
H6 gpmc_ben1 1501 0 1397 0 CFG_GPMC_BEN1_IN - vin2b_fld1
L4 gpmc_clk 0 0 0 0 CFG_GPMC_CLK_IN - vin2b_clk1
A6 gpmc_cs1 1192 0 1102 0 CFG_GPMC_CS1_IN - vin2b_vsync1
G3 gpmc_cs3 1324 374 1466 353 CFG_GPMC_CS3_IN vin1a_clk0 -

Manual IO Timings Modes must be used to ensure some IO timings for VIP1. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-36Manual Functions Mapping for VIN1B (IOSET6/7) for a definition of the Manual modes.

Table 5-36 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-36 Manual Functions Mapping for VIN1B (IOSET6/7)

BALL BALL NAME VIP_MANUAL9 VIP_MANUAL14 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 5 6
M1 gpmc_a0 1873 702 2202 441 CFG_GPMC_A0_IN - vin1b_d0
M2 gpmc_a1 1629 772 2057 413 CFG_GPMC_A1_IN - vin1b_d1
J2 gpmc_a10 0 0 0 0 CFG_GPMC_A10_IN - vin1b_clk1
L3 gpmc_a11 1851 1011 2126 856 CFG_GPMC_A11_IN - vin1b_de1
G1 gpmc_a12 2009 601 2289 327 CFG_GPMC_A12_IN - vin1b_fld1
L2 gpmc_a2 1734 898 2131 573 CFG_GPMC_A2_IN - vin1b_d2
L1 gpmc_a3 1757 1076 2106 812 CFG_GPMC_A3_IN - vin1b_d3
K3 gpmc_a4 1794 893 2164 559 CFG_GPMC_A4_IN - vin1b_d4
K2 gpmc_a5 1726 853 2120 523 CFG_GPMC_A5_IN - vin1b_d5
J1 gpmc_a6 1792 612 2153 338 CFG_GPMC_A6_IN - vin1b_d6
K1 gpmc_a7 2117 610 2389 304 CFG_GPMC_A7_IN - vin1b_d7
K4 gpmc_a8 1758 653 2140 308 CFG_GPMC_A8_IN - vin1b_hsync1
H1 gpmc_a9 1705 899 2067 646 CFG_GPMC_A9_IN - vin1b_vsync1
L6 mdio_d 1945 671 2265 414 CFG_MDIO_D_IN vin1b_d0 -
L5 mdio_mclk 255 119 337 0 CFG_MDIO_MCLK_IN vin1b_clk1 -
N2 rgmii0_rxc 2057 909 2341 646 CFG_RGMII0_RXC_IN vin1b_d5 -
P2 rgmii0_rxctl 2121 1139 2323 988 CFG_RGMII0_RXCTL_IN vin1b_d6 -
N4 rgmii0_rxd0 2070 655 2336 340 CFG_RGMII0_RXD0_IN vin1b_fld1 -
N1 rgmii0_rxd3 2092 1357 2306 1216 CFG_RGMII0_RXD3_IN vin1b_d7 -
T4 rgmii0_txc 2088 1205 2328 1079 CFG_RGMII0_TXC_IN vin1b_d3 -
T5 rgmii0_txctl 2143 1383 2312 1311 CFG_RGMII0_TXCTL_IN vin1b_d4 -
R2 rgmii0_txd1 2078 1189 2324 1065 CFG_RGMII0_TXD1_IN vin1b_vsync1 -
P3 rgmii0_txd2 1928 1125 2306 763 CFG_RGMII0_TXD2_IN vin1b_hsync1 -
P4 rgmii0_txd3 2255 971 2401 846 CFG_RGMII0_TXD3_IN vin1b_de1 -
N5 uart3_rxd 1829 747 2220 400 CFG_UART3_RXD_IN vin1b_d1 -
N6 uart3_txd 2030 837 2324 568 CFG_UART3_TXD_IN vin1b_d2 -

Manual IO Timings Modes must be used to ensure some IO timings for VIP1. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-37Manual Functions Mapping for VIN2B (IOSET2/11) for a definition of the Manual modes.

Table 5-37 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-37 Manual Functions Mapping for VIN2B (IOSET2/11)

BALL BALL NAME VIP_MANUAL10 VIP_MANUAL11 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 4 6
A4 gpmc_a19 1600 943 2023 477 CFG_GPMC_A19_IN - vin2b_d0
E7 gpmc_a20 1440 621 1875 136 CFG_GPMC_A20_IN - vin2b_d1
D6 gpmc_a21 1602 1066 2021 604 CFG_GPMC_A21_IN - vin2b_d2
C5 gpmc_a22 1395 983 1822 519 CFG_GPMC_A22_IN - vin2b_d3
B5 gpmc_a23 1571 716 2045 200 CFG_GPMC_A23_IN - vin2b_d4
D7 gpmc_a24 1463 832 1893 396 CFG_GPMC_A24_IN - vin2b_d5
C6 gpmc_a25 1426 1166 1842 732 CFG_GPMC_A25_IN - vin2b_d6
A5 gpmc_a26 1362 1094 1797 584 CFG_GPMC_A26_IN - vin2b_d7
B6 gpmc_a27 1283 809 1760 338 CFG_GPMC_A27_IN - vin2b_hsync1
H2 gpmc_ben0 1978 780 2327 389 CFG_GPMC_BEN0_IN - vin2b_de1
H6 gpmc_ben1 0 0 0 0 CFG_GPMC_BEN1_IN vin2b_clk1 -
A6 gpmc_cs1 1411 982 1857 536 CFG_GPMC_CS1_IN - vin2b_vsync1

Manual IO Timings Modes must be used to ensure some IO timings for VIP1. See Table 5-29Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-38Manual Functions Mapping for VIN1A (IOSET8/9/10) for a definition of the Manual modes.

Table 5-38 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-38 Manual Functions Mapping for VIN1A (IOSET8/9/10)

BALL BALL NAME VIP_MANUAL15 VIP_MANUAL16 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 7 9
Y5 gpio6_10 2131 2198 2170 2180 CFG_GPIO6_10_IN - vin1a_clk0
Y6 gpio6_11 3720 2732 4106 2448 CFG_GPIO6_11_IN - vin1a_de0
C16 mcasp1_aclkx 2447 0 3042 0 CFG_MCASP1_ACLKX_IN vin1a_fld0 -
D14 mcasp1_axr0 3061 0 3380 292 CFG_MCASP1_AXR0_IN vin1a_vsync0 -
B14 mcasp1_axr1 3113 0 3396 304 CFG_MCASP1_AXR1_IN vin1a_hsync0 -
B16 mcasp1_axr10 2803 0 3362 0 CFG_MCASP1_AXR10_IN vin1a_d13 -
B18 mcasp1_axr11 3292 0 3357 546 CFG_MCASP1_AXR11_IN vin1a_d12 -
A19 mcasp1_axr12 2854 0 3145 320 CFG_MCASP1_AXR12_IN vin1a_d11 -
E17 mcasp1_axr13 2813 0 3229 196 CFG_MCASP1_AXR13_IN vin1a_d10 -
E16 mcasp1_axr14 2471 0 3053 0 CFG_MCASP1_AXR14_IN vin1a_d9 -
F16 mcasp1_axr15 2815 0 3225 201 CFG_MCASP1_AXR15_IN vin1a_d8 -
A18 mcasp1_axr8 2965 0 3427 83 CFG_MCASP1_AXR8_IN vin1a_d15 -
B17 mcasp1_axr9 3082 0 3253 440 CFG_MCASP1_AXR9_IN vin1a_d14 -
C17 mcasp1_fsx 2898 0 3368 139 CFG_MCASP1_FSX_IN vin1a_de0 -
E19 mcasp2_aclkx 2413 0 2972 0 CFG_MCASP2_ACLKX_IN vin1a_d7 -
A21 mcasp2_axr2 2478 0 3062 0 CFG_MCASP2_AXR2_IN vin1a_d5 -
B21 mcasp2_axr3 2806 0 3175 242 CFG_MCASP2_AXR3_IN vin1a_d4 -
D19 mcasp2_fsx 2861 78 2936 599 CFG_MCASP2_FSX_IN vin1a_d6 -
A22 mcasp3_aclkx 1583 0 1878 0 CFG_MCASP3_ACLKX_IN vin1a_d3 -
B22 mcasp3_axr0 2873 0 3109 375 CFG_MCASP3_AXR0_IN vin1a_d1 -
B23 mcasp3_axr1 1625 1400 2072 1023 CFG_MCASP3_AXR1_IN vin1a_d0 -
A23 mcasp3_fsx 2792 0 3146 257 CFG_MCASP3_FSX_IN vin1a_d2 -
Y2 mmc3_clk 3907 2744 4260 2450 CFG_MMC3_CLK_IN - vin1a_d7
Y1 mmc3_cmd 3892 2768 4242 2470 CFG_MMC3_CMD_IN - vin1a_d6
Y4 mmc3_dat0 3786 2765 4156 2522 CFG_MMC3_DAT0_IN - vin1a_d5
AA2 mmc3_dat1 3673 2961 4053 2667 CFG_MMC3_DAT1_IN - vin1a_d4
AA3 mmc3_dat2 3818 2447 4209 2096 CFG_MMC3_DAT2_IN - vin1a_d3
W2 mmc3_dat3 3902 2903 4259 2672 CFG_MMC3_DAT3_IN - vin1a_d2
Y3 mmc3_dat4 3905 2622 4259 2342 CFG_MMC3_DAT4_IN - vin1a_d1
AA1 mmc3_dat5 3807 2824 4167 2595 CFG_MMC3_DAT5_IN - vin1a_d0
AA4 mmc3_dat6 3724 2818 4123 2491 CFG_MMC3_DAT6_IN - vin1a_hsync0
AB1 mmc3_dat7 3775 2481 4159 2161 CFG_MMC3_DAT7_IN - vin1a_vsync0
J25 xref_clk0 1971 0 2472 0 CFG_XREF_CLK0_IN vin1a_d0 -
J24 xref_clk1 0 192 0 603 CFG_XREF_CLK1_IN vin1a_clk0 -