JAJSFR8E August   2016  – May 2019 DRA790 , DRA791 , DRA793 , DRA797

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  CSI2
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  HDQ1W
      10. 4.3.10 UART
      11. 4.3.11 McSPI
      12. 4.3.12 QSPI
      13. 4.3.13 McASP
      14. 4.3.14 USB
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 ATL
      25. 4.3.25 Emulation and Debug Subsystem
      26. 4.3.26 System and Miscellaneous
        1. 4.3.26.1 Sysboot
        2. 4.3.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.3.26.3 System Direct Memory Access (SDMA)
        4. 4.3.26.4 Interrupt Controllers (INTC)
      27. 4.3.27 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power on Hour (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS CSI2 DC Electrical Characteristics
      6. Table 5-11 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-12 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-13 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      USBPHY DC Electrical Characteristics
      10. 5.7.2      HDMIPHY DC Electrical Characteristics
      11. 5.7.3      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-14 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics for CBD Package
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.10.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RC On-die Oscillator Clock
        2. 5.10.4.2 Output Clocks
        3. 5.10.4.3 DPLLs, DLLs
          1. 5.10.4.3.1 DPLL Characteristics
          2. 5.10.4.3.2 DLL Characteristics
          3. 5.10.4.3.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  CSI2
          1. 5.10.6.6.1 CSI-2 MIPI D-PHY
        7. 5.10.6.7  EMIF
        8. 5.10.6.8  GPMC
          1. 5.10.6.8.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.8.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
        9. 5.10.6.9  Timers
        10. 5.10.6.10 I2C
          1. Table 5-56 Timing Requirements for I2C Input Timings
          2. Table 5-57 Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)
          3. Table 5-58 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        11. 5.10.6.11 HDQ1W
          1. 5.10.6.11.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.11.2 HDQ/1-Wire—1-Wire Mode
        12. 5.10.6.12 UART
          1. Table 5-63 Timing Requirements for UART
          2. Table 5-64 Switching Characteristics Over Recommended Operating Conditions for UART
        13. 5.10.6.13 McSPI
        14. 5.10.6.14 QSPI
        15. 5.10.6.15 McASP
          1. Table 5-71 Timing Requirements for McASP1
          2. Table 5-72 Timing Requirements for McASP2
          3. Table 5-73 Timing Requirements for McASP3/4/5/6/7/8
        16. 5.10.6.16 USB
          1. 5.10.6.16.1 USB1 DRD PHY
          2. 5.10.6.16.2 USB2 PHY
          3. 5.10.6.16.3 USB3 DRD ULPI—SDR—Slave Mode—12-pin Mode
        17. 5.10.6.17 PCIe
        18. 5.10.6.18 DCAN
          1. Table 5-91 Timing Requirements for DCANx Receive
          2. Table 5-92 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-93 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-94 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-95 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-96 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-101 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-102 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-103 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-104 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-108 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-109 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-111 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 MLB
        21. 5.10.6.21 eMMC/SD/SDIO
          1. 5.10.6.21.1 MMC1—SD Card Interface
            1. 5.10.6.21.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.21.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.21.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.21.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.21.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.21.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.21.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.21.2 MMC2 — eMMC
            1. 5.10.6.21.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.21.2.2 High-speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.21.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
            4. 5.10.6.21.2.4 High-speed JC64 DDR, 8-bit data
              1. Table 5-142 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
          3. 5.10.6.21.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.21.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.21.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.21.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.21.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.21.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        22. 5.10.6.22 GPIO
        23. 5.10.6.23 PRU-ICSS
          1. 5.10.6.23.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.23.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-164 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-165 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.23.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-166 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.23.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-167 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-168 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.23.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-169 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-170 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-171 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.23.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.23.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-172 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-173 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-174 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-175 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-176 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.23.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.23.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-177 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-178 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-179 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.23.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-180 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-181 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-182 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-183 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.23.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-184 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-185 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.23.5 PRU-ICSS IOSETs
          6. 5.10.6.23.6 PRU-ICSS Manual Functional Mapping
        24. 5.10.6.24 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-202 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-203 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-204 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-205 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 Trace Port Interface Unit (TPIU)
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  IPU
    6. 6.6  PRU-ICSS
    7. 6.7  Memory Subsystem
      1. 6.7.1 EMIF
      2. 6.7.2 GPMC
      3. 6.7.3 ELM
      4. 6.7.4 OCMC
    8. 6.8  Interprocessor Communication
      1. 6.8.1 MailBox
      2. 6.8.2 Spinlock
    9. 6.9  Interrupt Controller
    10. 6.10 EDMA
    11. 6.11 Peripherals
      1. 6.11.1  VIP
      2. 6.11.2  DSS
      3. 6.11.3  Timers
        1. 6.11.3.1 General-Purpose Timers
        2. 6.11.3.2 32-kHz Synchronized Timer (COUNTER_32K)
        3. 6.11.3.3 Watchdog Timer
      4. 6.11.4  I2C
      5. 6.11.5  UART
        1. 6.11.5.1 UART Features
        2. 6.11.5.2 IrDA Features
        3. 6.11.5.3 CIR Features
      6. 6.11.6  McSPI
      7. 6.11.7  QSPI
      8. 6.11.8  McASP
      9. 6.11.9  USB
      10. 6.11.10 PCIe
      11. 6.11.11 DCAN
      12. 6.11.12 GMAC_SW
      13. 6.11.13 eMMC/SD/SDIO
      14. 6.11.14 GPIO
      15. 6.11.15 ePWM
      16. 6.11.16 eCAP
      17. 6.11.17 eQEP
    12. 6.12 On-chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 Power Regulators
        3. 7.5.2.3 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 PCIe Board Design and Layout Guidelines
        1. 7.5.5.1 PCIe Connections and Interface Compliance
          1. 7.5.5.1.1 Coupling Capacitors
          2. 7.5.5.1.2 Polarity Inversion
        2. 7.5.5.2 Non-standard PCIe connections
          1. 7.5.5.2.1 PCB Stackup Specifications
          2. 7.5.5.2.2 Routing Specifications
            1. 7.5.5.2.2.1 Impedance
            2. 7.5.5.2.2.2 Differential Coupling
            3. 7.5.5.2.2.3 Pair Length Matching
        3. 7.5.5.3 LJCB_REFN/P Connections
      6. 7.5.6 CSI2 Board Design and Routing Guidelines
        1. 7.5.6.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.6.1.1 General Guidelines
          2. 7.5.6.1.2 Length Mismatch Guidelines
            1. 7.5.6.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.6.1.3 Frequency-domain Specification Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7 DDR3 Board Design and Layout Guidelines
      1. 7.7.1 DDR3 General Board Layout Guidelines
      2. 7.7.2 DDR3 Board Design and Layout Guidelines
        1. 7.7.2.1  Board Designs
        2. 7.7.2.2  DDR3 EMIF
        3. 7.7.2.3  DDR3 Device Combinations
        4. 7.7.2.4  DDR3 Interface Schematic
          1. 7.7.2.4.1 32-Bit DDR3 Interface
          2. 7.7.2.4.2 16-Bit DDR3 Interface
        5. 7.7.2.5  Compatible JEDEC DDR3 Devices
        6. 7.7.2.6  PCB Stackup
        7. 7.7.2.7  Placement
        8. 7.7.2.8  DDR3 Keepout Region
        9. 7.7.2.9  Bulk Bypass Capacitors
        10. 7.7.2.10 High-Speed Bypass Capacitors
          1. 7.7.2.10.1 Return Current Bypass Capacitors
        11. 7.7.2.11 Net Classes
        12. 7.7.2.12 DDR3 Signal Termination
        13. 7.7.2.13 VREF_DDR Routing
        14. 7.7.2.14 VTT
        15. 7.7.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.7.2.15.1 Four DDR3 Devices
            1. 7.7.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.7.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.7.2.15.2 Two DDR3 Devices
            1. 7.7.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.7.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.7.2.15.3 One DDR3 Device
            1. 7.7.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.7.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.7.2.16 Data Topologies and Routing Definition
          1. 7.7.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.7.2.17 Routing Specification
          1. 7.7.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.7.2.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • CBD|538
サーマルパッド・メカニカル・データ
発注情報

4.3.20 GPIO

NOTE

For more information, see the General-Purpose Interface section of the device TRM.

Table 4-21 GPIOs Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
GPIO 1
gpio1_0 General-Purpose Input I AC10
gpio1_3 General-Purpose Input I AB10
gpio1_4 General-Purpose Input/Output IO B20
gpio1_5 General-Purpose Input/Output IO C20
gpio1_6 General-Purpose Input/Output IO F1
gpio1_7 General-Purpose Input/Output IO E2
gpio1_8 General-Purpose Input/Output IO E1
gpio1_9 General-Purpose Input/Output IO C1
gpio1_10 General-Purpose Input/Output IO D1
gpio1_11 General-Purpose Input/Output IO D2
gpio1_12 General-Purpose Input/Output IO B1
gpio1_13 General-Purpose Input/Output IO B2
gpio1_14 General-Purpose Input/Output IO H22
gpio1_15 General-Purpose Input/Output IO H23
gpio1_16 General-Purpose Input/Output IO N22
gpio1_17 General-Purpose Input/Output IO N24
gpio1_18 General-Purpose Input/Output IO C3
gpio1_19 General-Purpose Input/Output IO C4
gpio1_20 General-Purpose Input/Output IO A3
gpio1_21 General-Purpose Input/Output IO B4
gpio1_22 General-Purpose Input/Output IO Y3
gpio1_23 General-Purpose Input/Output IO AA1
gpio1_24 General-Purpose Input/Output IO AA4
gpio1_25 General-Purpose Input/Output IO AB1
gpio1_26 General-Purpose Input/Output IO K3
gpio1_27 General-Purpose Input/Output IO K2
gpio1_28 General-Purpose Input/Output IO J1
gpio1_29 General-Purpose Input/Output IO K1
gpio1_30 General-Purpose Input/Output IO K4
gpio1_31 General-Purpose Input/Output IO H1
GPIO2
gpio2_0 General-Purpose Input/Output IO J2
gpio2_1 General-Purpose Input/Output IO L3
gpio2_2 General-Purpose Input/Output IO G1
gpio2_3 General-Purpose Input/Output IO H3
gpio2_4 General-Purpose Input/Output IO H4
gpio2_5 General-Purpose Input/Output IO K6
gpio2_6 General-Purpose Input/Output IO K5
gpio2_7 General-Purpose Input/Output IO G2
gpio2_8 General-Purpose Input/Output IO F2
gpio2_9 General-Purpose Input/Output IO A4
gpio2_10 General-Purpose Input/Output IO E7
gpio2_11 General-Purpose Input/Output IO D6
gpio2_12 General-Purpose Input/Output IO C5
gpio2_13 General-Purpose Input/Output IO B5
gpio2_14 General-Purpose Input/Output IO D7
gpio2_15 General-Purpose Input/Output IO C6
gpio2_16 General-Purpose Input/Output IO A5
gpio2_17 General-Purpose Input/Output IO B6
gpio2_18 General-Purpose Input/Output IO A6
gpio2_19 General-Purpose Input/Output IO F3
gpio2_20 General-Purpose Input/Output IO G4
gpio2_21 General-Purpose Input/Output IO G3
gpio2_22 General-Purpose Input/Output IO L4
gpio2_23 General-Purpose Input/Output IO H5
gpio2_24 General-Purpose Input/Output IO G5
gpio2_25 General-Purpose Input/Output IO G6
gpio2_26 General-Purpose Input/Output IO H2
gpio2_27 General-Purpose Input/Output IO H6
gpio2_28 General-Purpose Input/Output IO F6
gpio2_29 General-Purpose Input/Output IO D20
GPIO 3
gpio3_28 General-Purpose Input/Output IO D8
gpio3_29 General-Purpose Input/Output IO B7
gpio3_30 General-Purpose Input/Output IO C7
gpio3_31 General-Purpose Input/Output IO E8
GPIO 4
gpio4_0 General-Purpose Input/Output IO B8
gpio4_1 General-Purpose Input/Output IO C8
gpio4_2 General-Purpose Input/Output IO B9
gpio4_3 General-Purpose Input/Output IO A7
gpio4_4 General-Purpose Input/Output IO A9
gpio4_5 General-Purpose Input/Output IO A8
gpio4_6 General-Purpose Input/Output IO A11
gpio4_7 General-Purpose Input/Output IO F10
gpio4_8 General-Purpose Input/Output IO A10
gpio4_9 General-Purpose Input/Output IO B10
gpio4_10 General-Purpose Input/Output IO E10
gpio4_11 General-Purpose Input/Output IO D10
gpio4_12 General-Purpose Input/Output IO C10
gpio4_13 General-Purpose Input/Output IO B11
gpio4_14 General-Purpose Input/Output IO D11
gpio4_15 General-Purpose Input/Output IO C11
gpio4_16 General-Purpose Input/Output IO B12
gpio4_17 General-Purpose Input/Output IO B18
gpio4_18 General-Purpose Input/Output IO A19
gpio4_24 General-Purpose Input/Output IO A12
gpio4_25 General-Purpose Input/Output IO A13
gpio4_26 General-Purpose Input/Output IO E11
gpio4_27 General-Purpose Input/Output IO F11
gpio4_28 General-Purpose Input/Output IO B13
gpio4_29 General-Purpose Input/Output IO E13
gpio4_30 General-Purpose Input/Output IO C13
gpio4_31 General-Purpose Input/Output IO D13
GPIO 5
gpio5_0 General-Purpose Input/Output IO D16
gpio5_1 General-Purpose Input/Output IO D17
gpio5_2 General-Purpose Input/Output IO D14
gpio5_3 General-Purpose Input/Output IO B14
gpio5_4 General-Purpose Input/Output IO C14
gpio5_5 General-Purpose Input/Output IO B15
gpio5_6 General-Purpose Input/Output IO A15
gpio5_7 General-Purpose Input/Output IO A14
gpio5_8 General-Purpose Input/Output IO A17
gpio5_9 General-Purpose Input/Output IO A16
gpio5_10 General-Purpose Input/Output IO A18
gpio5_11 General-Purpose Input/Output IO B17
gpio5_12 General-Purpose Input/Output IO B16
gpio5_13 General-Purpose Input/Output IO A22
gpio5_14 General-Purpose Input/Output IO A23
gpio5_15 General-Purpose Input/Output IO L5
gpio5_16 General-Purpose Input/Output IO L6
gpio5_17 General-Purpose Input/Output IO P5
gpio5_18 General-Purpose Input/Output IO N5
gpio5_19 General-Purpose Input/Output IO N6
gpio5_20 General-Purpose Input/Output IO T4
gpio5_21 General-Purpose Input/Output IO T5
gpio5_22 General-Purpose Input/Output IO P4
gpio5_23 General-Purpose Input/Output IO P3
gpio5_24 General-Purpose Input/Output IO R2
gpio5_25 General-Purpose Input/Output IO R1
gpio5_26 General-Purpose Input/Output IO N2
gpio5_27 General-Purpose Input/Output IO P2
gpio5_28 General-Purpose Input/Output IO N1
gpio5_29 General-Purpose Input/Output IO P1
gpio5_30 General-Purpose Input/Output IO N3
gpio5_31 General-Purpose Input/Output IO N4
GPIO 6
gpio6_4 General-Purpose Input/Output IO E17
gpio6_5 General-Purpose Input/Output IO E16
gpio6_6 General-Purpose Input/Output IO F16
gpio6_7 General-Purpose Input/Output IO C19
gpio6_8 General-Purpose Input/Output IO A21
gpio6_9 General-Purpose Input/Output IO B21
gpio6_10 General-Purpose Input/Output IO Y5
gpio6_11 General-Purpose Input/Output IO Y6
gpio6_12 General-Purpose Input/Output IO AD3
gpio6_13 General-Purpose Input/Output IO AA6
gpio6_14 General-Purpose Input/Output IO H21
gpio6_15 General-Purpose Input/Output IO K22
gpio6_16 General-Purpose Input/Output IO K23
gpio6_17 General-Purpose Input/Output IO J25
gpio6_18 General-Purpose Input/Output IO J24
gpio6_19 General-Purpose Input/Output IO H24
gpio6_20 General-Purpose Input/Output IO H25
gpio6_21 General-Purpose Input/Output IO U3
gpio6_22 General-Purpose Input/Output IO V4
gpio6_23 General-Purpose Input/Output IO V3
gpio6_24 General-Purpose Input/Output IO V2
gpio6_25 General-Purpose Input/Output IO W1
gpio6_26 General-Purpose Input/Output IO V1
gpio6_27 General-Purpose Input/Output IO U5
gpio6_28 General-Purpose Input/Output IO V5
gpio6_29 General-Purpose Input/Output IO Y2
gpio6_30 General-Purpose Input/Output IO Y1
gpio6_31 General-Purpose Input/Output IO Y4
GPIO 7
gpio7_0 General-Purpose Input/Output IO AA2
gpio7_1 General-Purpose Input/Output IO AA3
gpio7_2 General-Purpose Input/Output IO W2
gpio7_3 General-Purpose Input/Output IO M1
gpio7_4 General-Purpose Input/Output IO M2
gpio7_5 General-Purpose Input/Output IO L2
gpio7_6 General-Purpose Input/Output IO L1
gpio7_7 General-Purpose Input/Output IO C24
gpio7_8 General-Purpose Input/Output IO D24
gpio7_9 General-Purpose Input/Output IO D25
gpio7_10 General-Purpose Input/Output IO B24
gpio7_11 General-Purpose Input/Output IO C25
gpio7_12 General-Purpose Input/Output IO E24
gpio7_13 General-Purpose Input/Output IO E25
gpio7_14 General-Purpose Input/Output IO G25
gpio7_15 General-Purpose Input/Output IO F25
gpio7_16 General-Purpose Input/Output IO G24
gpio7_17 General-Purpose Input/Output IO F24
gpio7_18 General-Purpose Input/Output IO C2
gpio7_19 General-Purpose Input/Output IO D3
gpio7_22 General-Purpose Input/Output IO L25
gpio7_23 General-Purpose Input/Output IO M25
gpio7_24 General-Purpose Input/Output IO L20
gpio7_25 General-Purpose Input/Output IO M24
gpio7_26 General-Purpose Input/Output IO N23
gpio7_27 General-Purpose Input/Output IO N25
gpio7_28 General-Purpose Input/Output IO A2
gpio7_29 General-Purpose Input/Output IO B3
gpio7_30 General-Purpose Input/Output IO C17
gpio7_31 General-Purpose Input/Output IO C16
GPIO 8
gpio8_27 General-Purpose Input I L23
gpio8_28 General-Purpose Input/Output IO J20
gpio8_29 General-Purpose Input/Output IO K25
gpio8_30(1) General-Purpose Input/Output IO C21
gpio8_31(1) General-Purpose Input/Output IO C22
  1. gpio8_30 is multiplexed with EMU0 and gpio8_31 is multiplexed with EMU1. These pins will be sampled at reset release by the test and emulation logic. Therefore, if they are used as GPIO pins, they must return to the high state whenever the device enters reset. This can be controlled by logic driven from rstoutn. After the device exits reset (indicated by rstoutn rising), these can return to GPIO mode.