JAJSFR8 データシート

JAJSFR8E August 2016 – May 2019 DRA790 , DRA791 , DRA793 , DRA797

PRODUCTION DATA.

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

CBD|538

サーマルパッド・メカニカル・データ

発注情報

jajsfr8e_oa

5.10.4.1.3.2 OSC1 Input Clock

A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the SYS_CLK2 clock input to the system. The external connections to support this are shown in, Figure 5-18. The xi_osc1 pin is connected to the 1.8-V LVCMOS-Compatible clock sources. The xo_osc1 pin is left unconnected. The vssa_osc1 pin is connected to board ground (vss).

DRA790 DRA791 DRA793 DRA797 SPRS906_CLK_07.gif

Figure 5-18 1.8-V LVCMOS-Compatible Clock Input

Table 5-23 summarizes the OSC1 input clock electrical characteristics.

Table 5-23 OSC1 Input Clock Electrical Characteristics—Bypass Mode

NAME	DESCRIPTION	MIN	TYP	MAX	UNIT
f	Frequency	Range from 12 to 38.4			MHz
C_IN	Input capacitance	2.819	3.019	3.219	pF
I_IN	Input current (3.3V mode)	4	6	10	µA
t_sX	Start-up time^⁽¹⁾	See^⁽²⁾			ms

To switch from bypass mode to crystal or from crystal mode to bypass mode, there is a waiting time about 100 μs; however, if the chip comes from bypass mode to crystal mode the crystal will start-up after time mentioned in Table 5-22, t_sX parameter.
Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in application mode and receives a wave. The switching time in this case is about 100 μs.

Table 5-24 details the OSC1 input clock timing requirements.

Table 5-24 OSC1 Input Clock Timing Requirements

NAME	DESCRIPTION			MIN	MAX	UNIT
CK0	1 / t_c(xiosc1)	Frequency, xi_osc1		Range from 12 to 38.4		MHz
CK1	t_w(xiosc1)	Pulse duration, xi_osc1 low or high		0.45 × t_c(xiosc1)	0.55 × t_c(xiosc1)	ns
	t_j(xiosc1)	Period jitter^⁽¹⁾, xi_osc1			0.01 × t_c(xiosc1)^⁽³⁾	ns
	t_R(xiosc1)	Rise time, xi_osc1			5	ns
	t_F(xiosc1)	Fall time, xi_osc1			5	ns
	t_j(xiosc1)	Frequency accuracy^⁽²⁾, xi_osc1	Ethernet and MLB not used		±200	ppm
			Ethernet RGMII and RMII using derived clock		±50
			Ethernet MII using derived clock		±100
			MLB using derived clock		±50

Period jitter is meant here as follows:
- The maximum value is the difference between the longest measured clock period and the expected clock period
- The minimum value is the difference between the shortest measured clock period and the expected clock period
Crystal characteristics should account for tolerance+stability+aging.
The Period jitter requirement for osc1 can be relaxed to 0.02 × tc(xiosc1) under the following constraints:
a.The osc1/SYS_CLK2 clock bypasses all device PLLs
b.The osc1/SYS_CLK2 clock is only used to source the DSS pixel clock outputs

DRA790 DRA791 DRA793 DRA797 SPRS906_CLK_08.gif

Figure 5-19 xi_osc1 Input Clock