JAJSKY8K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1
PRODUCTION DATA
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Table 6-82, Figure 6-99, Table 6-83, and Figure 6-100 present timing requirements and switching characteristics for MMC1/2 – High Speed Mode.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
HS1 | tsu(cmdV-clkH) | Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge | 2.55 | ns | |
HS2 | th(clkH-cmdV) | Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge | 2.67 | ns | |
HS3 | tsu(dV-clkH) | Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge | 2.55 | ns | |
HS4 | th(clkH-dV) | Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge | 2.67 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fop(clk) | Operating frequency, MMC[x]_CLK | 50 | MHz | ||
HS5 | tc(clk) | Cycle time. MMC[x]_CLK | 20 | ns | |
HS6 | tw(clkH) | Pulse duration, MMC[x]_CLK high | 9.2 | ns | |
HS7 | tw(clkL) | Pulse duration, MMC[x]_CLK low | 9.2 | ns | |
HS8 | td(clkL-cmdV) | Delay time, MMC[x]_CLK falling edge to MMC[x]_CMD transition | -1.77 | 2.35 | ns |
HS9 | td(clkL-dV) | Delay time, MMC[x]_CLK falling edge to MMC[x]_DAT[3:0] transition | -1.77 | 2.35 | ns |