JAJSKY8K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
Table 6-80, Figure 6-92, Table 6-81, and Figure 6-93 present timing requirements and switching characteristics for MMC1/2 – Default Speed Mode.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
DS1 | tsu(cmdV-clkH) | Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge | 2.55 | ns | |
DS2 | th(clkH-cmdV) | Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge | 4.65 | ns | |
DS3 | tsu(dV-clkH) | Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge | 2.55 | ns | |
DS4 | th(clkH-dV) | Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge | 4.65 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fop(clk) | Operating frequency, MMC[x]_CLK | 25 | MHz | ||
DS5 | tc(clk) | Cycle time, MMC[x]_CLK | 40 | ns | |
DS6 | tw(clkH) | Pulse duration, MMC[x]_CLK high | 18.7 | ns | |
DS7 | tw(clkL) | Pulse duration, MMC[x]_CLK low | 18.7 | ns | |
DS8 | td(clkL-cmdV) | Delay time, MMC[x]_CLK falling edge to MMC[x]_CMD transition | -2.93 | 3.63 | ns |
DS9 | td(clkL-dV) | Delay time, MMC[x]_CLK falling edge to MMC[x]_DAT[3:0] transition | -2.93 | 3.63 | ns |