JAJSKY8K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1
PRODUCTION DATA
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Table 6-84, Figure 6-101, Table 6-85, and Figure 6-102 present timing requirements and switching characteristics for MMC1/2 – UHS-I SDR12 Mode.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
SDR121 | tsu(cmdV-clkH) | Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge | 21.65 | ns | |
SDR122 | th(clkH-cmdV) | Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge | 1.67 | ns | |
SDR123 | tsu(dV-clkH) | Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge | 21.65 | ns | |
SDR124 | th(clkH-dV) | Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge | 1.67 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fop(clk) | Operating frequency, MMC[x]_CLK | 25 | MHz | ||
SDR125 | tc(clk) | Cycle time, MMC[x]_CLK | 40 | ns | |
SDR126 | tw(clkH) | Pulse duration, MMC[x]_CLK high | 18.7 | ns | |
SDR127 | tw(clkL) | Pulse duration, MMC[x]_CLK low | 18.7 | ns | |
SDR128 | td(clkH-cmdV) | Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition | 1.2 | 13.69 | ns |
SDR129 | td(clkH-dV) | Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition | 1.2 | 13.69 | ns |