JAJSKY8K February   2019  – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1. 3.1 機能ブロック図
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
      2. 5.3.2  DDRSS
        1. 5.3.2.1 MAIN Domain
      3. 5.3.3  GPIO
        1. 5.3.3.1 MAIN Domain
        2. 5.3.3.2 WKUP Domain
      4. 5.3.4  I2C
        1. 5.3.4.1 MAIN Domain
        2. 5.3.4.2 MCU Domain
        3. 5.3.4.3 WKUP Domain
      5. 5.3.5  I3C
        1. 5.3.5.1 MAIN Domain
        2. 5.3.5.2 MCU Domain
      6. 5.3.6  MCAN
        1. 5.3.6.1 MAIN Domain
        2. 5.3.6.2 MCU Domain
      7. 5.3.7  MCSPI
        1. 5.3.7.1 MAIN Domain
        2. 5.3.7.2 MCU Domain
      8. 5.3.8  UART
        1. 5.3.8.1 MAIN Domain
        2. 5.3.8.2 MCU Domain
        3. 5.3.8.3 WKUP Domain
      9. 5.3.9  MDIO
        1. 5.3.9.1 MCU Domain
      10. 5.3.10 CPSW2G
        1. 5.3.10.1 MCU Domain
      11. 5.3.11 CPSW9G
        1. 5.3.11.1 MAIN Domain
      12. 5.3.12 ECAP
        1. 5.3.12.1 MAIN Domain
      13. 5.3.13 EQEP
        1. 5.3.13.1 MAIN Domain
      14. 5.3.14 EHRPWM
        1. 5.3.14.1 MAIN Domain
      15. 5.3.15 USB
        1. 5.3.15.1 MAIN Domain
      16. 5.3.16 SERDES
        1. 5.3.16.1 MAIN Domain
      17. 5.3.17 OSPI
        1. 5.3.17.1 MCU Domain
      18. 5.3.18 Hyperbus
        1. 5.3.18.1 MCU Domain
      19. 5.3.19 GPMC
        1. 5.3.19.1 MAIN Domain
      20. 5.3.20 MMC
        1. 5.3.20.1 MAIN Domain
      21. 5.3.21 CPTS
        1. 5.3.21.1 MCU Domain
        2. 5.3.21.2 MAIN Domain
      22. 5.3.22 UFS
        1. 5.3.22.1 MAIN Domain
      23. 5.3.23 PRU_ICSSG [Currently Not Supported]
        1. 5.3.23.1 MAIN Domain
      24. 5.3.24 MCASP
        1. 5.3.24.1 MAIN Domain
      25. 5.3.25 DSS
        1. 5.3.25.1 MAIN Domain
      26. 5.3.26 DP
        1. 5.3.26.1 MAIN Domain
      27. 5.3.27 Camera Streaming Interface Receiver (CSI_RX_IF) Subsystem
        1. 5.3.27.1 MAIN Domain
      28. 5.3.28 DSI_TX
        1. 5.3.28.1 MAIN Domain
      29. 5.3.29 VPFE
        1. 5.3.29.1 MAIN Domain
      30. 5.3.30 DMTIMER
        1. 5.3.30.1 MAIN Domain
        2. 5.3.30.2 MCU Domain
      31. 5.3.31 Emulation and Debug
        1. 5.3.31.1 MAIN Domain
      32. 5.3.32 System and Miscellaneous
        1. 5.3.32.1 Boot Mode Configuration
          1. 5.3.32.1.1 MAIN Domain
          2. 5.3.32.1.2 MCU Domain
        2. 5.3.32.2 Clock
          1. 5.3.32.2.1 MAIN Domain
          2. 5.3.32.2.2 WKUP Domain
        3. 5.3.32.3 System
          1. 5.3.32.3.1 MAIN Domain
          2. 5.3.32.3.2 WKUP Domain
        4. 5.3.32.4 EFUSE
      33. 5.3.33 Power Supply
    4. 5.4 Pin Multiplexing
    5. 5.5 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Power-On-Hour (POH) Limits
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Operating Performance Points
    6. 6.6 Electrical Characteristics
      1. 6.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 6.6.3  HFOSC/LFOSC Electrical Characteristics
      4. 6.6.4  eMMCPHY Electrical Characteristics
      5. 6.6.5  SDIO Electrical Characteristics
      6. 6.6.6  CSI-2/DSI D-PHY Electrical Characteristics
      7. 6.6.7  ADC12B Electrical Characteristics
      8. 6.6.8  MLB LVCMOS Electrical Characteristics
      9. 6.6.9  LVCMOS Electrical Characteristics
      10. 6.6.10 USB2PHY Electrical Characteristics
      11. 6.6.11 SerDes 4-L-PHY/2-L-PHY Electrical Characteristics
      12. 6.6.12 UFS M-PHY Electrical Characteristics
      13. 6.6.13 eDP/DP AUX-PHY Electrical Characteristics
      14. 6.6.14 DDR0 Electrical Characteristics
    7. 6.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8 Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics for ALF Package
    9. 6.9 Timing and Switching Characteristics
      1. 6.9.1 Timing Parameters and Information
      2. 6.9.2 Power Supply Sequencing
        1. 6.9.2.1 Power Supply Slew Rate Requirement
        2. 6.9.2.2 Combined MCU and Main Domains Power-Up Sequencing
        3. 6.9.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 6.9.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 6.9.2.5 Isolated MCU and Main Domains, Primary Power- Down Sequencing
        6. 6.9.2.6 Entry and Exit of MCU Only State
        7. 6.9.2.7 Entry and Exit of DDR Retention State
      3. 6.9.3 System Timing
        1. 6.9.3.1 Reset Timing
        2. 6.9.3.2 Safety Signal Timing
        3. 6.9.3.3 Clock Timing
      4. 6.9.4 Clock Specifications
        1. 6.9.4.1 Input and Output Clocks / Oscillators
          1. 6.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 6.9.4.1.1.1 Load Capacitance
            2. 6.9.4.1.1.2 Shunt Capacitance
          2. 6.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 6.9.4.1.3.1 Load Capacitance
            2. 6.9.4.1.3.2 Shunt Capacitance
          4. 6.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.9.4.1.5 Auxiliary OSC1 Not Used
          6. 6.9.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
            1. 6.9.4.1.6.1 WKUP_LFOSC0 Not Used
        2. 6.9.4.2 Output Clocks
        3. 6.9.4.3 PLLs
        4. 6.9.4.4 Module and Peripheral Clocks Frequencies
      5. 6.9.5 Peripherals
        1. 6.9.5.1  ATL
          1. 6.9.5.1.1 ATL_PCLK Timing Requirements
          2. 6.9.5.1.2 ATL_AWS[x] Timing Requirements
          3. 6.9.5.1.3 ATL_BWS[x] Timing Requirements
          4. 6.9.5.1.4 ATCLK[x] Switching Characteristics
        2. 6.9.5.2  VPFE
        3. 6.9.5.3  CPSW2G
          1. 6.9.5.3.1 CPSW2G MDIO Interface Timings
          2. 6.9.5.3.2 CPSW2G RMII Timings
            1. 6.9.5.3.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.9.5.3.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.9.5.3.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 6.9.5.3.3 CPSW2G RGMII Timings
            1. 6.9.5.3.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.9.5.3.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 6.9.5.3.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.9.5.3.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        4. 6.9.5.4  CPSW9G
          1. 6.9.5.4.1 CPSW9G MDIO Interface Timings
          2. 6.9.5.4.2 CPSW9G RMII Timings
            1. 6.9.5.4.2.1 RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.9.5.4.2.2 RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.9.5.4.2.3 RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics – RMII Mode
          3. 6.9.5.4.3 CPSW9G RGMII Timings
            1. 6.9.5.4.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.9.5.4.3.2 RGMII[x]_RD[3:0] and RGMII[x]_RCTL Timing Requirements – RGMII Mode
            3. 6.9.5.4.3.3 RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.9.5.4.3.4 RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        5. 6.9.5.5  CSI-2
        6. 6.9.5.6  DDRSS
        7. 6.9.5.7  DSS
        8. 6.9.5.8  eCAP
          1. 6.9.5.8.1 Timing Requirements for eCAP
          2. 6.9.5.8.2 Switching Characteristics for eCAP
        9. 6.9.5.9  EPWM
          1. 6.9.5.9.1 Timing Requirements for eHRPWM
          2. 6.9.5.9.2 Switching Characteristics for eHRPWM
        10. 6.9.5.10 eQEP
          1. 6.9.5.10.1 Timing Requirements for eQEP
          2. 6.9.5.10.2 Switching Characteristics for eQEP
        11. 6.9.5.11 GPIO
          1. 6.9.5.11.1 GPIO Timing Requirements
          2. 6.9.5.11.2 GPIO Switching Characteristics
        12. 6.9.5.12 GPMC
          1. 6.9.5.12.1 GPMC and NOR Flash — Synchronous Mode
            1. 6.9.5.12.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 6.9.5.12.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 6.9.5.12.2 GPMC and NOR Flash — Asynchronous Mode
            1. 6.9.5.12.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 6.9.5.12.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 6.9.5.12.3 GPMC and NAND Flash — Asynchronous Mode
            1. 6.9.5.12.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 6.9.5.12.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 6.9.5.12.4 GPMC0 IOSET
        13. 6.9.5.13 HyperBus
          1. 6.9.5.13.1 Timing Requirements for HyperBus
          2. 6.9.5.13.2 HyperBus 166 MHz Switching Characteristics
          3. 6.9.5.13.3 HyperBus 100 MHz Switching Characteristics
        14. 6.9.5.14 I2C
        15. 6.9.5.15 I3C
        16. 6.9.5.16 MCAN
        17. 6.9.5.17 MCASP
        18. 6.9.5.18 MCSPI
          1. 6.9.5.18.1 MCSPI — Master Mode
          2. 6.9.5.18.2 MCSPI — Slave Mode
        19. 6.9.5.19 MMCSD
          1. 6.9.5.19.1 MMC0 - eMMC Interface
            1. 6.9.5.19.1.1 Legacy SDR Mode
            2. 6.9.5.19.1.2 High Speed SDR Mode
            3. 6.9.5.19.1.3 High Speed DDR Mode
            4. 6.9.5.19.1.4 HS200 Mode
          2. 6.9.5.19.2 MMC1/2 - SD/SDIO Interface
            1. 6.9.5.19.2.1 Default Speed Mode
            2. 6.9.5.19.2.2 High Speed Mode
            3. 6.9.5.19.2.3 UHS–I SDR12 Mode
            4. 6.9.5.19.2.4 UHS–I SDR25 Mode
            5. 6.9.5.19.2.5 UHS–I SDR50 Mode
            6. 6.9.5.19.2.6 UHS–I DDR50 Mode
            7. 6.9.5.19.2.7 UHS–I SDR104 Mode
        20. 6.9.5.20 CPTS
          1. 6.9.5.20.1 CPTS Timing Requirements
          2. 6.9.5.20.2 CPTS Switching Characteristics
        21. 6.9.5.21 OSPI
          1. 6.9.5.21.1 OSPI PHY Mode
            1. 6.9.5.21.1.1 OSPI With Data Training
              1. 6.9.5.21.1.1.1 OSPI Switching Characteristics – Data Training
            2. 6.9.5.21.1.2 OSPI Without Data Training
              1. 6.9.5.21.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 6.9.5.21.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 6.9.5.21.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 6.9.5.21.1.2.4 OSPI Switching Characteristics – DDR Mode
          2. 6.9.5.21.2 OSPI Tap Mode
            1. 6.9.5.21.2.1 OSPI Tap SDR Timing
            2. 6.9.5.21.2.2 OSPI Tap DDR Timing
        22. 6.9.5.22 PCIE
        23. 6.9.5.23 Timers
          1. 6.9.5.23.1 Timing Requirements for Timers
          2. 6.9.5.23.2 Switching Characteristics for Timers
        24. 6.9.5.24 UART
          1. 6.9.5.24.1 Timing Requirements for UART
          2. 6.9.5.24.2 UART Switching Characteristics
        25. 6.9.5.25 USB
      6. 6.9.6 Emulation and Debug
        1. 6.9.6.1 Trace
        2. 6.9.6.2 JTAG
          1. 6.9.6.2.1 JTAG Electrical Data and Timing
            1. 6.9.6.2.1.1 JTAG Timing Requirements
            2. 6.9.6.2.1.2 JTAG Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A72
      2. 7.2.2 Arm Cortex-R5F
      3. 7.2.3 DSP C71x
      4. 7.2.4 DSP C66x
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 GPU
      2. 7.3.2 D5520MP2
      3. 7.3.3 VXE384MP2
    4. 7.4 Other Subsystems
      1. 7.4.1 MSMC
      2. 7.4.2 NAVSS
        1. 7.4.2.1 NAVSS0
        2. 7.4.2.2 MCU_NAVSS
      3. 7.4.3 PDMA Controller
      4. 7.4.4 Power Supply
      5. 7.4.5 Peripherals
        1. 7.4.5.1  ADC
        2. 7.4.5.2  ATL
        3. 7.4.5.3  CSI
          1. 7.4.5.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 7.4.5.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        4. 7.4.5.4  CPSW2G
        5. 7.4.5.5  CPSW9G
        6. 7.4.5.6  DCC
        7. 7.4.5.7  DDRSS
        8. 7.4.5.8  DSS
          1. 7.4.5.8.1 DSI
          2. 7.4.5.8.2 eDP
        9. 7.4.5.9  VPFE
        10. 7.4.5.10 eCAP
        11. 7.4.5.11 EPWM
        12. 7.4.5.12 ELM
        13. 7.4.5.13 ESM
        14. 7.4.5.14 eQEP
        15. 7.4.5.15 GPIO
        16. 7.4.5.16 GPMC
        17. 7.4.5.17 Hyperbus
        18. 7.4.5.18 I2C
        19. 7.4.5.19 I3C
        20. 7.4.5.20 MCAN
        21. 7.4.5.21 MCASP
        22. 7.4.5.22 MCRC Controller
        23. 7.4.5.23 MCSPI
        24. 7.4.5.24 MMC/SD
        25. 7.4.5.25 OSPI
        26. 7.4.5.26 PCIE
        27. 7.4.5.27 SerDes
        28. 7.4.5.28 WWDT
        29. 7.4.5.29 Timers
        30. 7.4.5.30 UART
        31. 7.4.5.31 USB
        32. 7.4.5.32 UFS
  9. 8 Applications and Implementation
    1. 8.1 Power Supply Mapping
    2. 8.2 Device Connection and Layout Fundamentals
      1. 8.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 8.2.1.1 Power Distribution Network Implementation Guidance
      2. 8.2.2 External Oscillator
      3. 8.2.3 JTAG and EMU
      4. 8.2.4 Reset
      5. 8.2.5 Unused Pins
      6. 8.2.6 Hardware Design Guide for JacintoTM 7 Devices
    3. 8.3 Peripheral- and Interface-Specific Design Information
      1. 8.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 8.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 8.3.2.1 No Loopback and Internal Pad Loopback
        2. 8.3.2.2 External Board Loopback
        3. 8.3.2.3 DQS (only available in Octal Flash devices)
      3. 8.3.3 SERDES REFCLK Design Guidelines
      4. 8.3.4 USB VBUS Design Guidelines
      5. 8.3.5 System Power Supply Monitor Design Guidelines
      6. 8.3.6 High Speed Differential Signal Routing Guidance
      7. 8.3.7 Thermal Solution Guidance
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ALF|827
サーマルパッド・メカニカル・データ
発注情報

5.2 Pin Attributes

Note:

MCU_BOOTMODE pins are latched on the rising edge of MCU_PORz_OUT. BOOTMODE pins are latched on the rising edge of PORz_OUT.

Note:

Media Local Bus (MLB) is not available on this device. The following balls must be left unconnected if not used in GPIO mode: AE2, AD2, AD3, AC3, AC1, AD1.

Note:

PRU_ICSSG0 and PRU_ICSSG1 are not available on this device. The prg* signals should not be used. Those pins can be used for other functions.

Table 5-1 Pin Attributes
BALL
NO. 1		 BALL NAME 2 SIGNAL NAME 3 MUXMODE 4 TYPE 5 BALL RESET STATE 6 BALL RESET REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/DOWN TYPE 12 DSIS 13 RXACTIVE/TXDISABLE 14
U7 CAP_VDDS0 CAP_VDDS0 CAP
K23 CAP_VDDS0_MCU CAP_VDDS0_MCU CAP
AB21 CAP_VDDS1 CAP_VDDS1 CAP
J18 CAP_VDDS1_MCU CAP_VDDS1_MCU CAP
Y18 CAP_VDDS2 CAP_VDDS2 CAP
J19 CAP_VDDS2_MCU CAP_VDDS2_MCU CAP
W21 CAP_VDDS3 CAP_VDDS3 CAP
AA22 CAP_VDDS4 CAP_VDDS4 CAP
R22 CAP_VDDS5 CAP_VDDS5 CAP
V22 CAP_VDDS6 CAP_VDDS6 CAP
B20 CSI0_RXCLKN CSI0_RXCLKN I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
A21 CSI0_RXCLKP CSI0_RXCLKP I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
F16 csi0_rxrcalib CSI0_RXRCALIB A OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
F15 csi1_rxrcalib CSI1_RXRCALIB A OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
B17 CSI1_RXCLKN CSI1_RXCLKN I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
A18 CSI1_RXCLKP CSI1_RXCLKP I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
B19 CSI0_RXN0 CSI0_RXN0 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
D18 CSI0_RXN1 CSI0_RXN1 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
D17 CSI0_RXN2 CSI0_RXN2 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
E16 CSI0_RXN3 CSI0_RXN3 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
A20 CSI0_RXP0 CSI0_RXP0 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
C19 CSI0_RXP1 CSI0_RXP1 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
C18 CSI0_RXP2 CSI0_RXP2 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
E17 CSI0_RXP3 CSI0_RXP3 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
B16 CSI1_RXN0 CSI1_RXN0 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
D15 CSI1_RXN1 CSI1_RXN1 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
D14 CSI1_RXN2 CSI1_RXN2 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
E13 CSI1_RXN3 CSI1_RXN3 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
A17 CSI1_RXP0 CSI1_RXP0 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
C16 CSI1_RXP1 CSI1_RXP1 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
C15 CSI1_RXP2 CSI1_RXP2 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
E14 CSI1_RXP3 CSI1_RXP3 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
J1 ddr0_ckn DDR0_CKN IO OFF 1.1 V VDDS_DDR DDR0
H1 ddr0_ckp DDR0_CKP IO OFF 1.1 V VDDS_DDR DDR0
K6 ddr0_resetn DDR0_RESETn IO OFF 1.1 V VDDS_DDR DDR0
G4 ddr0_ca0 DDR0_CA0 IO OFF 1.1 V VDDS_DDR DDR0
H3 ddr0_ca1 DDR0_CA1 IO OFF 1.1 V VDDS_DDR DDR0
K5 ddr0_ca2 DDR0_CA2 IO OFF 1.1 V VDDS_DDR DDR0
J4 ddr0_ca3 DDR0_CA3 IO OFF 1.1 V VDDS_DDR DDR0
K2 ddr0_ca4 DDR0_CA4 IO OFF 1.1 V VDDS_DDR DDR0
H5 ddr0_ca5 DDR0_CA5 IO OFF 1.1 V VDDS_DDR DDR0
H2 ddr0_cal0 DDR0_CAL0 A OFF 1.1 V VDDS_DDR DDR0
G3 ddr0_cke0 DDR0_CKE0 IO OFF 1.1 V VDDS_DDR DDR0
J3 ddr0_cke1 DDR0_CKE1 IO OFF 1.1 V VDDS_DDR DDR0
J5 ddr0_csn0_0 DDR0_CSn0_0 IO OFF 1.1 V VDDS_DDR DDR0
K3 ddr0_csn0_1 DDR0_CSn0_1 IO OFF 1.1 V VDDS_DDR DDR0
G5 ddr0_csn1_0 DDR0_CSn1_0 IO OFF 1.1 V VDDS_DDR DDR0
J2 ddr0_csn1_1 DDR0_CSn1_1 IO OFF 1.1 V VDDS_DDR DDR0
A3 ddr0_dm0 DDR0_DM0 IO OFF 1.1 V VDDS_DDR DDR0
E4 ddr0_dm1 DDR0_DM1 IO OFF 1.1 V VDDS_DDR DDR0
N1 ddr0_dm2 DDR0_DM2 IO OFF 1.1 V VDDS_DDR DDR0
R5 ddr0_dm3 DDR0_DM3 IO OFF 1.1 V VDDS_DDR DDR0
A5 ddr0_dq0 DDR0_DQ0 IO OFF 1.1 V VDDS_DDR DDR0
A6 ddr0_dq1 DDR0_DQ1 IO OFF 1.1 V VDDS_DDR DDR0
B5 ddr0_dq2 DDR0_DQ2 IO OFF 1.1 V VDDS_DDR DDR0
C2 ddr0_dq3 DDR0_DQ3 IO OFF 1.1 V VDDS_DDR DDR0
B4 ddr0_dq4 DDR0_DQ4 IO OFF 1.1 V VDDS_DDR DDR0
C3 ddr0_dq5 DDR0_DQ5 IO OFF 1.1 V VDDS_DDR DDR0
A2 ddr0_dq6 DDR0_DQ6 IO OFF 1.1 V VDDS_DDR DDR0
A4 ddr0_dq7 DDR0_DQ7 IO OFF 1.1 V VDDS_DDR DDR0
D1 ddr0_dq8 DDR0_DQ8 IO OFF 1.1 V VDDS_DDR DDR0
C4 ddr0_dq9 DDR0_DQ9 IO OFF 1.1 V VDDS_DDR DDR0
F1 ddr0_dq10 DDR0_DQ10 IO OFF 1.1 V VDDS_DDR DDR0
G2 ddr0_dq11 DDR0_DQ11 IO OFF 1.1 V VDDS_DDR DDR0
F2 ddr0_dq12 DDR0_DQ12 IO OFF 1.1 V VDDS_DDR DDR0
F3 ddr0_dq13 DDR0_DQ13 IO OFF 1.1 V VDDS_DDR DDR0
D3 ddr0_dq14 DDR0_DQ14 IO OFF 1.1 V VDDS_DDR DDR0
F5 ddr0_dq15 DDR0_DQ15 IO OFF 1.1 V VDDS_DDR DDR0
L5 ddr0_dq16 DDR0_DQ16 IO OFF 1.1 V VDDS_DDR DDR0
M5 ddr0_dq17 DDR0_DQ17 IO OFF 1.1 V VDDS_DDR DDR0
N5 ddr0_dq18 DDR0_DQ18 IO OFF 1.1 V VDDS_DDR DDR0
L4 ddr0_dq19 DDR0_DQ19 IO OFF 1.1 V VDDS_DDR DDR0
L2 ddr0_dq20 DDR0_DQ20 IO OFF 1.1 V VDDS_DDR DDR0
L1 ddr0_dq21 DDR0_DQ21 IO OFF 1.1 V VDDS_DDR DDR0
N2 ddr0_dq22 DDR0_DQ22 IO OFF 1.1 V VDDS_DDR DDR0
N4 ddr0_dq23 DDR0_DQ23 IO OFF 1.1 V VDDS_DDR DDR0
T3 ddr0_dq24 DDR0_DQ24 IO OFF 1.1 V VDDS_DDR DDR0
T2 ddr0_dq25 DDR0_DQ25 IO OFF 1.1 V VDDS_DDR DDR0
P2 ddr0_dq26 DDR0_DQ26 IO OFF 1.1 V VDDS_DDR DDR0
P3 ddr0_dq27 DDR0_DQ27 IO OFF 1.1 V VDDS_DDR DDR0
P5 ddr0_dq28 DDR0_DQ28 IO OFF 1.1 V VDDS_DDR DDR0
R4 ddr0_dq29 DDR0_DQ29 IO OFF 1.1 V VDDS_DDR DDR0
T4 ddr0_dq30 DDR0_DQ30 IO OFF 1.1 V VDDS_DDR DDR0
T5 ddr0_dq31 DDR0_DQ31 IO OFF 1.1 V VDDS_DDR DDR0
B1 ddr0_dqs0n DDR0_DQS0N IO OFF 1.1 V VDDS_DDR DDR0
B2 ddr0_dqs0p DDR0_DQS0P IO OFF 1.1 V VDDS_DDR DDR0
E2 ddr0_dqs1n DDR0_DQS1N IO OFF 1.1 V VDDS_DDR DDR0
E3 ddr0_dqs1p DDR0_DQS1P IO OFF 1.1 V VDDS_DDR DDR0
M2 ddr0_dqs2n DDR0_DQS2N IO OFF 1.1 V VDDS_DDR DDR0
M3 ddr0_dqs2p DDR0_DQS2P IO OFF 1.1 V VDDS_DDR DDR0
R1 ddr0_dqs3n DDR0_DQS3N IO OFF 1.1 V VDDS_DDR DDR0
R2 ddr0_dqs3p DDR0_DQS3P IO OFF 1.1 V VDDS_DDR DDR0
P6 ddr_ret DDR_RET I OFF 1.1 V VDDS_DDR_BIAS DDR0
G6 dp0_auxn DP0_AUXN IO OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP AUX-PHY
F7 dp0_auxp DP0_AUXP IO OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP AUX-PHY
E10 DSI_TXCLKN DSI_TXCLKN O OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
CSI0_TXCLKN O
E11 DSI_TXCLKP DSI_TXCLKP O OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
CSI0_TXCLKP O
D11 DSI_TXN0 DSI_TXN0 IO OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
CSI0_TXN0 O
D12 DSI_TXN1 DSI_TXN1 O OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
CSI0_TXN1 O
B13 DSI_TXN2 DSI_TXN2 O OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
CSI0_TXN2 O
B14 DSI_TXN3 DSI_TXN3 O OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
CSI0_TXN3 O
C12 DSI_TXP0 DSI_TXP0 IO OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
CSI0_TXP0 O
C13 DSI_TXP1 DSI_TXP1 O OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
CSI0_TXP1 O
A14 DSI_TXP2 DSI_TXP2 O OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
CSI0_TXP2 O
A15 DSI_TXP3 DSI_TXP3 O OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
CSI0_TXP3 O
F12 dsi_txrcalib DSI_TXRCALIB A OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
U2 ecap0_in_apwm_out ECAP0_IN_APWM_OUT 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1
SYNC0_OUT 1 O
CPTS0_RFT_CLK 2 I 0
SPI2_CS3 4 IO 1
I3C0_SDAPULLEN 5 O
SPI7_CS0 6 IO 1
GPIO1_11 7 IO 0
C26 emu0 EMU0 0 IO PU 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1/1
B29 emu1 EMU1 0 IO PU 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1/1
AC18 extintn EXTINTn 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes I2C OD FS 1 0/0
GPIO0_0 7 IO 0
U3 ext_refclk1 EXT_REFCLK1 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1
SYNC1_OUT 1 O
SPI7_CLK 6 IO 0
GPIO1_12 7 IO 0
AC5 i2c0_scl I2C0_SCL 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes I2C OD FS 1 1/0
GPIO1_7 7 IO 0
AA5 i2c0_sda I2C0_SDA 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes I2C OD FS 1 1/0
GPIO1_8 7 IO 0
Y6 i2c1_scl I2C1_SCL 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes I2C OD FS 1 1/0
CPTS0_HW1TSPUSH 1 I 0
GPIO1_9 7 IO 0
AA6 i2c1_sda I2C1_SDA 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes I2C OD FS 1 1/0
CPTS0_HW2TSPUSH 1 I 0
GPIO1_10 7 IO 0
W2 i3c0_scl I3C0_SCL 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1
MMC2_SDCD 1 I 1
UART9_CTSn 2 I 1
MCAN2_RX 3 I 1
I2C6_SCL 4 IOD 1
DP0_HPD 5 I 0
PCIE0_CLKREQn 6 IO 0
GPIO1_5 7 IO 0
UART6_RXD 8 I 0
W1 i3c0_sda I3C0_SDA 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1
MMC2_SDWP 1 I 1
UART9_RTSn 2 O
MCAN2_TX 3 O
I2C6_SDA 4 IOD 1
PCIE1_CLKREQn 6 IO 0
GPIO1_6 7 IO 0
UART6_TXD 8 O 0
W5 mcan0_rx MCAN0_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1
I2C2_SCL 4 IOD 1
GPIO1_1 7 IO 0
W6 mcan0_tx MCAN0_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1
I2C2_SDA 4 IOD 1
GPIO1_2 7 IO 0
W3 mcan1_rx MCAN1_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1
UART6_CTSn 1 I 1
UART9_RXD 2 I 1
USB0_DRVVBUS 3 O
USB1_DRVVBUS 4 O
GPIO1_3 7 IO 0
V4 mcan1_tx MCAN1_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1
UART6_RTSn 1 O
UART9_TXD 2 O
USB0_DRVVBUS 3 O
USB1_DRVVBUS 4 O
GPIO1_4 7 IO 0
K25 mcu_adc0_ain0 MCU_ADC0_AIN0 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B
WKUP_GPIO0_68 -1 I
K26 mcu_adc0_ain1 MCU_ADC0_AIN1 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B
WKUP_GPIO0_69 -1 I
K28 mcu_adc0_ain2 MCU_ADC0_AIN2 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B
WKUP_GPIO0_70 -1 I
L28 mcu_adc0_ain3 MCU_ADC0_AIN3 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B
WKUP_GPIO0_71 -1 I
K24 mcu_adc0_ain4 MCU_ADC0_AIN4 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B
WKUP_GPIO0_72 -1 I
K27 mcu_adc0_ain5 MCU_ADC0_AIN5 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B
WKUP_GPIO0_73 -1 I
K29 mcu_adc0_ain6 MCU_ADC0_AIN6 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B
WKUP_GPIO0_74 -1 I
L29 mcu_adc0_ain7 MCU_ADC0_AIN7 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B
WKUP_GPIO0_75 -1 I
N23 mcu_adc1_ain0 MCU_ADC1_AIN0 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B
WKUP_GPIO0_76 -1 I
M25 mcu_adc1_ain1 MCU_ADC1_AIN1 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B
WKUP_GPIO0_77 -1 I
L24 mcu_adc1_ain2 MCU_ADC1_AIN2 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B
WKUP_GPIO0_78 -1 I
L26 mcu_adc1_ain3 MCU_ADC1_AIN3 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B
WKUP_GPIO0_79 -1 I
N24 mcu_adc1_ain4 MCU_ADC1_AIN4 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B
WKUP_GPIO0_80 -1 I
M24 mcu_adc1_ain5 MCU_ADC1_AIN5 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B
WKUP_GPIO0_81 -1 I
L25 mcu_adc1_ain6 MCU_ADC1_AIN6 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B
WKUP_GPIO0_82 -1 I
L27 mcu_adc1_ain7 MCU_ADC1_AIN7 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B
WKUP_GPIO0_83 -1 I
J26 mcu_i2c0_scl MCU_I2C0_SCL 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes I2C OD FS 1 1/0
WKUP_GPIO0_64 7 IO 0
H25 mcu_i2c0_sda MCU_I2C0_SDA 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes I2C OD FS 1 1/0
WKUP_GPIO0_65 7 IO 0
D26 mcu_i3c0_scl MCU_I3C0_SCL 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 0/1
MCU_UART0_CTSn 2 I 1
MCU_TIMER_IO8 4 IO 0
WKUP_GPIO0_60 7 IO 0
D25 mcu_i3c0_sda MCU_I3C0_SDA 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 0/1
MCU_UART0_RTSn 2 O
MCU_TIMER_IO9 4 IO 0
WKUP_GPIO0_61 7 IO 0
C29 mcu_mcan0_rx MCU_MCAN0_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 0/1
WKUP_GPIO0_59 7 IO 0
D29 mcu_mcan0_tx MCU_MCAN0_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0/1
WKUP_GPIO0_58 7 IO 0
F23 mcu_mdio0_mdc MCU_MDIO0_MDC 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0/1
WKUP_GPIO0_51 7 IO 0
E23 mcu_mdio0_mdio MCU_MDIO0_MDIO 0 IO OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 0/1
WKUP_GPIO0_50 7 IO 0
E20 mcu_ospi0_clk MCU_OSPI0_CLK 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0/1
MCU_HYPERBUS0_CK 1 O
WKUP_GPIO0_16 7 IO 0
D21 mcu_ospi0_dqs MCU_OSPI0_DQS 0 I OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_RWDS 1 IO 0
WKUP_GPIO0_18 7 IO 0
C21 mcu_ospi0_lbclko MCU_OSPI0_LBCLKO 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 1/1
MCU_HYPERBUS0_CKn 1 O
WKUP_GPIO0_17 7 IO 0
F22 mcu_ospi1_clk MCU_OSPI1_CLK 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0/1
WKUP_GPIO0_29 7 IO 0
B23 mcu_ospi1_dqs MCU_OSPI1_DQS 0 I OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_OSPI0_CSn3 1 O
MCU_HYPERBUS0_INTn 2 I 1
MCU_OSPI0_ECC_FAIL 6 I 1
WKUP_GPIO0_31 7 IO 0
A23 mcu_ospi1_lbclko MCU_OSPI1_LBCLKO 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 1/1
MCU_OSPI0_CSn2 1 O
MCU_HYPERBUS0_RESETOn 2 I 1
MCU_OSPI0_RESET_OUT0 6 O
WKUP_GPIO0_30 7 IO 0
F19 mcu_ospi0_csn0 MCU_OSPI0_CSn0 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0/1
MCU_HYPERBUS0_CSn0 1 O
WKUP_GPIO0_27 7 IO 0
E19 mcu_ospi0_csn1 MCU_OSPI0_CSn1 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0/1
MCU_HYPERBUS0_RESETn 1 O
WKUP_GPIO0_28 7 IO 0
D20 mcu_ospi0_d0 MCU_OSPI0_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_DQ0 1 IO 0
WKUP_GPIO0_19 7 IO 0
G19 mcu_ospi0_d1 MCU_OSPI0_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_DQ1 1 IO 0
WKUP_GPIO0_20 7 IO 0
G20 mcu_ospi0_d2 MCU_OSPI0_D2 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_DQ2 1 IO 0
WKUP_GPIO0_21 7 IO 0
F20 mcu_ospi0_d3 MCU_OSPI0_D3 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_DQ3 1 IO 0
WKUP_GPIO0_22 7 IO 0
F21 mcu_ospi0_d4 MCU_OSPI0_D4 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_DQ4 1 IO 0
WKUP_GPIO0_23 7 IO 0
E21 mcu_ospi0_d5 MCU_OSPI0_D5 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_DQ5 1 IO 0
WKUP_GPIO0_24 7 IO 0
B22 mcu_ospi0_d6 MCU_OSPI0_D6 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_DQ6 1 IO 0
WKUP_GPIO0_25 7 IO 0
G21 mcu_ospi0_d7 MCU_OSPI0_D7 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_DQ7 1 IO 0
WKUP_GPIO0_26 7 IO 0
C22 mcu_ospi1_csn0 MCU_OSPI1_CSn0 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0/1
WKUP_GPIO0_36 7 IO 0
E22 mcu_ospi1_csn1 MCU_OSPI1_CSn1 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0/1
MCU_HYPERBUS0_WPn 1 O
MCU_TIMER_IO0 2 IO 0
MCU_HYPERBUS0_CSn1 3 O
MCU_UART0_RTSn 4 O
MCU_SPI0_CS2 5 IO 1
MCU_OSPI0_RESET_OUT1 6 O
WKUP_GPIO0_37 7 IO 0
D22 mcu_ospi1_d0 MCU_OSPI1_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
WKUP_GPIO0_32 7 IO 0
G22 mcu_ospi1_d1 MCU_OSPI1_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_UART0_RXD 4 I 1
MCU_SPI1_CS1 5 IO 1
WKUP_GPIO0_33 7 IO 0
D23 mcu_ospi1_d2 MCU_OSPI1_D2 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_UART0_TXD 4 O
MCU_SPI1_CS2 5 IO 1
WKUP_GPIO0_34 7 IO 0
C23 mcu_ospi1_d3 MCU_OSPI1_D3 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_UART0_CTSn 4 I 1
MCU_SPI0_CS1 5 IO 1
WKUP_GPIO0_35 7 IO 0
H23 mcu_porz MCU_PORz I OFF 1.8 V VDDA_WKUP Yes FS Reset PU/PD
B28 mcu_porz_out MCU_PORz_OUT 0 O OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0/0
C27 mcu_resetstatz MCU_RESETSTATz 0 O OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0/0
D28 mcu_resetz MCU_RESETz 0 I PU 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1/1
C24 mcu_rgmii1_rxc MCU_RGMII1_RXC 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 0/1
MCU_RMII1_REF_CLK 1 I 0
WKUP_GPIO0_45 7 IO 0
C25 mcu_rgmii1_rx_ctl MCU_RGMII1_RX_CTL 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 0/1
MCU_RMII1_RX_ER 1 I 0
WKUP_GPIO0_39 7 IO 0
B26 mcu_rgmii1_txc MCU_RGMII1_TXC 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 0/1
MCU_RMII1_TX_EN 1 O
WKUP_GPIO0_44 7 IO 0
B27 mcu_rgmii1_tx_ctl MCU_RGMII1_TX_CTL 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0/1
MCU_RMII1_CRS_DV 1 I 0
WKUP_GPIO0_38 7 IO 0
B24 mcu_rgmii1_rd0 MCU_RGMII1_RD0 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 0/1
MCU_RMII1_RXD0 1 I 0
WKUP_GPIO0_49 7 IO 0
A24 mcu_rgmii1_rd1 MCU_RGMII1_RD1 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 0/1
MCU_RMII1_RXD1 1 I 0
WKUP_GPIO0_48 7 IO 0
D24 mcu_rgmii1_rd2 MCU_RGMII1_RD2 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 0/1
MCU_TIMER_IO5 1 IO 0
WKUP_GPIO0_47 7 IO 0
A25 mcu_rgmii1_rd3 MCU_RGMII1_RD3 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 0/1
MCU_TIMER_IO4 1 IO 0
WKUP_GPIO0_46 7 IO 0
B25 mcu_rgmii1_td0 MCU_RGMII1_TD0 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0/1
MCU_RMII1_TXD0 1 O
WKUP_GPIO0_43 7 IO 0
A26 mcu_rgmii1_td1 MCU_RGMII1_TD1 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0/1
MCU_RMII1_TXD1 1 O
WKUP_GPIO0_42 7 IO 0
A27 mcu_rgmii1_td2 MCU_RGMII1_TD2 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0/1
MCU_TIMER_IO3 1 IO 0
MCU_ADC_EXT_TRIGGER1 3 I 0
WKUP_GPIO0_41 7 IO 0
A28 mcu_rgmii1_td3 MCU_RGMII1_TD3 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0/1
MCU_TIMER_IO2 1 IO 0
MCU_ADC_EXT_TRIGGER0 3 I 0
WKUP_GPIO0_40 7 IO 0
D27 mcu_safety_errorn MCU_SAFETY_ERRORn 0 IO PD 0 1.8 V VDDA_WKUP Yes LVCMOS PU/PD 1/0
E27 mcu_spi0_clk MCU_SPI0_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 1/1
WKUP_GPIO0_52 7 IO 0
MCU_BOOTMODE00 Bootstrap I
E25 mcu_spi0_cs0 MCU_SPI0_CS0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 0/1
MCU_TIMER_IO1 4 IO 0
WKUP_GPIO0_55 7 IO 0
E24 mcu_spi0_d0 MCU_SPI0_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 1/1
WKUP_GPIO0_53 7 IO 0
MCU_BOOTMODE01 Bootstrap I
E28 mcu_spi0_d1 MCU_SPI0_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 1/1
MCU_TIMER_IO0 4 IO 0
WKUP_GPIO0_54 7 IO 0
MCU_BOOTMODE02 Bootstrap I
V24 mdio0_mdc MDIO0_MDC 0 O OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0/1
TRC_DATA23 5 O
GPIO0_110 7 IO 0
GPMC0_WAIT2 8 I 0
V26 mdio0_mdio MDIO0_MDIO 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1
TRC_DATA22 5 O
GPIO0_109 7 IO 0
GPMC0_WAIT3 8 I 0
AE2 mlb0_mlbcn MLB0_MLBCN 0 I OFF 0 1.8 V VDDA_1P8_MLB MLB_LVDS
GPIO1_35 7 IO 0
AD2 mlb0_mlbcp MLB0_MLBCP 0 I OFF 0 1.8 V VDDA_1P8_MLB MLB_LVDS
GPIO1_34 7 IO 0
AD3 mlb0_mlbdn MLB0_MLBDN 0 IO OFF 0 1.8 V VDDA_1P8_MLB MLB_LVDS
GPIO1_33 7 IO 0
AC3 mlb0_mlbdp MLB0_MLBDP 0 IO OFF 0 1.8 V VDDA_1P8_MLB MLB_LVDS
GPIO1_32 7 IO 0
AC1 mlb0_mlbsn MLB0_MLBSN 0 IO OFF 0 1.8 V VDDA_1P8_MLB MLB_LVDS
GPIO1_31 7 IO 0
AD1 mlb0_mlbsp MLB0_MLBSP 0 IO OFF 0 1.8 V VDDA_1P8_MLB MLB_LVDS
GPIO1_30 7 IO 0
AE1 mmc0_calpad MMC0_CALPAD A OFF 1.8 V VDDS_MMC0 eMMCPHY PU/PD
AF1 mmc0_clk MMC0_CLK O DRIVE 0 (OFF) 1.8 V VDDS_MMC0 eMMCPHY PU/PD
AE3 mmc0_cmd MMC0_CMD IO DRIVE 1 (OFF) 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
AE4 mmc0_ds MMC0_DS IO PD 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
P25 mmc1_clk MMC1_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 0 0/1
UART8_RXD 1 I 1
I2C4_SCL 4 IOD 1
GPIO1_19 7 IO 0
R29 mmc1_cmd MMC1_CMD 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1 0/1
UART8_TXD 1 O
I2C4_SDA 4 IOD 1
GPIO1_20 7 IO 0
P23 mmc1_sdcd MMC1_SDCD 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 1 0/1
UART8_CTSn 1 I 1
UART0_DCDn 2 I 1
TIMER_IO2 3 IO 0
EQEP2_I 5 IO 0
PCIE2_CLKREQn 6 IO 0
GPIO1_21 7 IO 0
PRG0_IEP0_EDC_LATCH_IN1 8 I 0
R28 mmc1_sdwp MMC1_SDWP 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 1 0/1
UART8_RTSn 1 O
UART0_DSRn 2 I 1
TIMER_IO3 3 IO 0
ECAP2_IN_APWM_OUT 4 IO 0
EQEP2_S 5 IO 0
PCIE3_CLKREQn 6 IO 0
GPIO1_22 7 IO 0
PRG0_IEP0_EDC_SYNC_OUT1 8 O 0
T26 mmc2_clk MMC2_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 0 0/1
USB0_DRVVBUS 1 O
USB1_DRVVBUS 2 O
TIMER_IO6 3 IO 0
I2C3_SCL 4 IOD 1
UART3_RXD 5 I 1
GPIO1_27 7 IO 0
T25 mmc2_cmd MMC2_CMD 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 1 0/1
USB0_DRVVBUS 1 O
USB1_DRVVBUS 2 O
TIMER_IO7 3 IO 0
I2C3_SDA 4 IOD 1
UART3_TXD 5 O
GPIO1_28 7 IO 0
AG2 mmc0_dat0 MMC0_DAT0 IO PU 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
AH1 mmc0_dat1 MMC0_DAT1 IO PU 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
AG3 mmc0_dat2 MMC0_DAT2 IO PU 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
AF4 mmc0_dat3 MMC0_DAT3 IO PU 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
AE5 mmc0_dat4 MMC0_DAT4 IO PU 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
AF3 mmc0_dat5 MMC0_DAT5 IO PU 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
AG1 mmc0_dat6 MMC0_DAT6 IO PU 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
AF2 mmc0_dat7 MMC0_DAT7 IO PU 1.8 V VDDS_MMC0 eMMCPHY 1
R24 mmc1_dat0 MMC1_DAT0 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1 0/1
UART7_RTSn 1 O
ECAP1_IN_APWM_OUT 2 IO 0
TIMER_IO1 3 IO 0
UART4_TXD 5 O
GPIO1_18 7 IO 0
P24 mmc1_dat1 MMC1_DAT1 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1 0/1
UART7_CTSn 1 I 1
ECAP0_IN_APWM_OUT 2 IO 0
TIMER_IO0 3 IO 0
UART4_RXD 5 I 1
GPIO1_17 7 IO 0
R25 mmc1_dat2 MMC1_DAT2 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1 0/1
UART7_TXD 1 O
GPIO1_16 7 IO 0
R26 mmc1_dat3 MMC1_DAT3 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1 0/1
UART7_RXD 1 I 1
GPIO1_15 7 IO 0
T24 mmc2_dat0 MMC2_DAT0 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 1 0/1
UART9_RTSn 1 O
UART0_RIn 2 I 1
TIMER_IO5 3 IO 0
UART6_TXD 4 O
EQEP2_B 5 I 0
GPIO1_26 7 IO 0
PRG0_IEP1_EDC_SYNC_OUT1 8 O 0
T27 mmc2_dat1 MMC2_DAT1 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 1 0/1
UART9_CTSn 1 I 1
UART0_DTRn 2 O
TIMER_IO4 3 IO 0
UART6_RXD 4 I 1
EQEP2_A 5 I 0
GPIO1_25 7 IO 0
PRG0_IEP1_EDC_LATCH_IN1 8 I 0
T29 mmc2_dat2 MMC2_DAT2 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 1 0/1
UART9_TXD 1 O
CPTS0_HW2TSPUSH 2 I 0
I2C5_SDA 4 IOD 1
GPIO1_24 7 IO 0
T28 mmc2_dat3 MMC2_DAT3 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 1 0/1
UART9_RXD 1 I 1
CPTS0_HW1TSPUSH 2 I 0
I2C5_SCL 4 IOD 1
GPIO1_23 7 IO 0
P29 osc1_xi OSC1_XI I OFF 1.8 V VDDS_OSC1 HFOSC
P27 osc1_xo OSC1_XO O OFF 1.8 V VDDS_OSC1 HFOSC
AE17 pcie_refclk0n PCIE_REFCLK0N IO OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
AD16 pcie_refclk0p PCIE_REFCLK0P IO OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
AE14 pcie_refclk1n PCIE_REFCLK1N IO OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
AD15 pcie_refclk1p PCIE_REFCLK1P IO OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
AE11 pcie_refclk2n PCIE_REFCLK2N IO OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
AD12 pcie_refclk2p PCIE_REFCLK2P IO OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
AE9 pcie_refclk3n PCIE_REFCLK3N IO OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
AD10 pcie_refclk3p PCIE_REFCLK3P IO OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
E26 pmic_power_en0 MCU_I3C0_SDAPULLEN 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0/0
WKUP_GPIO0_66 7 IO 0
G23 pmic_power_en1 PMIC_POWER_EN1 0 O OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0/0
MCU_I3C1_SDAPULLEN 5 O
WKUP_GPIO0_67 7 IO 0
J24 porz PORz 0 I OFF 0 1.8 V VDDA_WKUP Yes FS Reset PU/PD
U1 porz_out PORz_OUT 0 O OFF 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/0
AA27 prg0_mdio0_mdc PRG0_MDIO0_MDC 0 O OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0/1
I2C5_SDA 2 IOD 1
MCAN13_RX 6 I 1
GPIO0_84 7 IO 0
GPMC0_A0 8 OZ 0
DSS_FSYNC2 10 O
MCASP2_ACLKR 12 IO
MCASP2_AXR5 13 IO 0
Y26 prg0_mdio0_mdio PRG0_MDIO0_MDIO 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
I2C5_SCL 2 IOD 1
MCAN13_TX 6 O
GPIO0_83 7 IO 0
GPMC0_A27 8 OZ 0
DSS_FSYNC0 10 O
MCASP2_AFSR 12 IO
MCASP2_AXR4 13 IO 0
AF28 prg0_pru0_gpo0 PRG0_PRU0_GPO0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI0 1 I 0
PRG0_RGMII1_RD0 2 I 0
PRG0_PWM3_A0 3 IO 0
RGMII3_RD0 4 I 0
RMII3_RXD1 5 I 0
GPIO0_43 7 IO 0
MCASP0_AXR0 12 IO
AE28 prg0_pru0_gpo1 PRG0_PRU0_GPO1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI1 1 I 0
PRG0_RGMII1_RD1 2 I 0
PRG0_PWM3_B0 3 IO 1
RGMII3_RD1 4 I 0
RMII3_RXD0 5 I 0
GPIO0_44 7 IO 0
MCASP0_AXR1 12 IO
AE27 prg0_pru0_gpo2 PRG0_PRU0_GPO2 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI2 1 I 0
PRG0_RGMII1_RD2 2 I 0
PRG0_PWM2_A0 3 IO 0
RGMII3_RD2 4 I 0
RMII3_CRS_DV 5 I 0
GPIO0_45 7 IO 0
UART3_RXD 8 I 0
MCASP0_ACLKR 12 IO
AD26 prg0_pru0_gpo3 PRG0_PRU0_GPO3 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI3 1 I 0
PRG0_RGMII1_RD3 2 I 0
PRG0_PWM3_A2 3 IO 0
RGMII3_RD3 4 I 0
RMII3_RX_ER 5 I 0
GPIO0_46 7 IO 0
UART3_TXD 8 O 0
MCASP0_AFSR 12 IO
AD25 prg0_pru0_gpo4 PRG0_PRU0_GPO4 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI4 1 I 0
PRG0_RGMII1_RX_CTL 2 I 0
PRG0_PWM2_B0 3 IO 1
RGMII3_RX_CTL 4 I 0
RMII3_TXD1 5 O
GPIO0_47 7 IO 0
MCASP0_AXR2 12 IO
AC29 prg0_pru0_gpo5 PRG0_PRU0_GPO5 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 1/1
PRG0_PRU0_GPI5 1 I 0
PRG0_PWM3_B2 3 IO 1
RMII3_TXD0 5 O
GPIO0_48 7 IO 0
GPMC0_AD0 8 IO 0
MCASP0_AXR3 12 IO
BOOTMODE2 Bootstrap I
AE26 prg0_pru0_gpo6 PRG0_PRU0_GPO6 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI6 1 I 0
PRG0_RGMII1_RXC 2 I 0
PRG0_PWM3_A1 3 IO 0
RGMII3_RXC 4 I 0
RMII3_TX_EN 5 O
GPIO0_49 7 IO 0
MCASP0_AXR4 12 IO
AC28 prg0_pru0_gpo7 PRG0_PRU0_GPO7 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI7 1 I 0
PRG0_IEP0_EDC_LATCH_IN1 2 I 0
PRG0_PWM3_B1 3 IO 1
PRG0_ECAP0_SYNC_IN 4 I 0
MCAN9_TX 6 O
GPIO0_50 7 IO 0
GPMC0_AD1 8 IO 0
MCASP0_AXR5 12 IO
AC27 prg0_pru0_gpo8 PRG0_PRU0_GPO8 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI8 1 I 0
PRG0_PWM2_A1 3 IO 0
MCAN9_RX 6 I 1
GPIO0_51 7 IO 0
GPMC0_AD2 8 IO 0
MCASP0_AXR6 12 IO
UART6_RXD 14 I
AB26 prg0_pru0_gpo9 PRG0_PRU0_GPO9 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI9 1 I 0
PRG0_UART0_CTSn 2 I 1
PRG0_PWM3_TZ_IN 3 I 0
SPI3_CS1 4 IO 1
PRG0_IEP0_EDIO_DATA_IN_OUT28 5 IO 0
MCAN10_TX 6 O
GPIO0_52 7 IO 0
GPMC0_AD3 8 IO 0
MCASP0_ACLKX 12 IO
UART6_TXD 14 O
AB25 prg0_pru0_gpo10 PRG0_PRU0_GPO10 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI10 1 I 0
PRG0_UART0_RTSn 2 O
PRG0_PWM2_B1 3 IO 1
SPI3_CS2 4 IO 1
PRG0_IEP0_EDIO_DATA_IN_OUT29 5 IO 0
MCAN10_RX 6 I 1
GPIO0_53 7 IO 0
GPMC0_AD4 8 IO 0
MCASP0_AFSX 12 IO
AJ28 prg0_pru0_gpo11 PRG0_PRU0_GPO11 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI11 1 I 0
PRG0_RGMII1_TD0 2 O
PRG0_PWM3_TZ_OUT 3 O
RGMII3_TD0 4 O
GPIO0_54 7 IO 0
CLKOUT 9 OZ
MCASP0_AXR7 12 IO
AH27 prg0_pru0_gpo12 PRG0_PRU0_GPO12 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI12 1 I 0
PRG0_RGMII1_TD1 2 O
PRG0_PWM0_A0 3 IO 0
RGMII3_TD1 4 O
GPIO0_55 7 IO 0
DSS_FSYNC0 10 O
MCASP0_AXR8 12 IO
AH29 prg0_pru0_gpo13 PRG0_PRU0_GPO13 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI13 1 I 0
PRG0_RGMII1_TD2 2 O
PRG0_PWM0_B0 3 IO 1
RGMII3_TD2 4 O
GPIO0_56 7 IO 0
DSS_FSYNC2 10 O
MCASP0_AXR9 12 IO
AG28 prg0_pru0_gpo14 PRG0_PRU0_GPO14 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI14 1 I 0
PRG0_RGMII1_TD3 2 O
PRG0_PWM0_A1 3 IO 0
RGMII3_TD3 4 O
GPIO0_57 7 IO 0
UART4_RXD 8 I 0
MCASP0_AXR10 12 IO
AG27 prg0_pru0_gpo15 PRG0_PRU0_GPO15 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI15 1 I 0
PRG0_RGMII1_TX_CTL 2 O
PRG0_PWM0_B1 3 IO 1
RGMII3_TX_CTL 4 O
GPIO0_58 7 IO 0
UART4_TXD 8 O 0
DSS_FSYNC3 10 O
MCASP0_AXR11 12 IO
AH28 prg0_pru0_gpo16 PRG0_PRU0_GPO16 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI16 1 I 0
PRG0_RGMII1_TXC 2 IO 0
PRG0_PWM0_A2 3 IO 0
RGMII3_TXC 4 O 0
GPIO0_59 7 IO 0
DSS_FSYNC1 10 O
MCASP0_AXR12 12 IO
AB24 prg0_pru0_gpo17 PRG0_PRU0_GPO17 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 1/1
PRG0_PRU0_GPI17 1 I 0
PRG0_IEP0_EDC_SYNC_OUT1 2 O
PRG0_PWM0_B2 3 IO 1
PRG0_ECAP0_SYNC_OUT 4 O
GPIO0_60 7 IO 0
GPMC0_AD5 8 IO 0
OBSCLK1 9 O 0
MCASP0_AXR13 12 IO
BOOTMODE7 Bootstrap I
AB29 prg0_pru0_gpo18 PRG0_PRU0_GPO18 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI18 1 I 0
PRG0_IEP0_EDC_LATCH_IN0 2 I 0
PRG0_PWM0_TZ_IN 3 I 0
PRG0_ECAP0_IN_APWM_OUT 4 IO 0
GPIO0_61 7 IO 0
GPMC0_AD6 8 IO 0
MCASP0_AXR14 12 IO
AB28 prg0_pru0_gpo19 PRG0_PRU0_GPO19 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI19 1 I 0
PRG0_IEP0_EDC_SYNC_OUT0 2 O
PRG0_PWM0_TZ_OUT 3 O
GPIO0_62 7 IO 0
GPMC0_AD7 8 IO 0
MCASP0_AXR15 12 IO
AE29 prg0_pru1_gpo0 PRG0_PRU1_GPO0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI0 1 I 0
PRG0_RGMII2_RD0 2 I 0
RGMII4_RD0 4 I 0
RMII4_RXD0 5 I 0
GPIO0_63 7 IO 0
UART4_CTSn 8 I 0
MCASP1_AXR0 12 IO
UART5_RXD 14 I
AD28 prg0_pru1_gpo1 PRG0_PRU1_GPO1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI1 1 I 0
PRG0_RGMII2_RD1 2 I 0
RGMII4_RD1 4 I 0
RMII4_RXD1 5 I 0
GPIO0_64 7 IO 0
UART4_RTSn 8 O 0
MCASP1_AXR1 12 IO
UART5_TXD 14 O
AD27 prg0_pru1_gpo2 PRG0_PRU1_GPO2 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI2 1 I 0
PRG0_RGMII2_RD2 2 I 0
PRG0_PWM2_A2 3 IO 0
RGMII4_RD2 4 I 0
RMII4_CRS_DV 5 I 0
GPIO0_65 7 IO 0
GPMC0_A23 8 OZ 0
MCASP1_ACLKR 12 IO
MCASP1_AXR10 13 IO 0
AC25 prg0_pru1_gpo3 PRG0_PRU1_GPO3 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI3 1 I 0
PRG0_RGMII2_RD3 2 I 0
RGMII4_RD3 4 I 0
RMII4_RX_ER 5 I 0
GPIO0_66 7 IO 0
MCASP1_AFSR 12 IO
MCASP1_AXR11 13 IO 0
AD29 prg0_pru1_gpo4 PRG0_PRU1_GPO4 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI4 1 I 0
PRG0_RGMII2_RX_CTL 2 I 0
PRG0_PWM2_B2 3 IO 1
RGMII4_RX_CTL 4 I 0
RMII4_TXD1 5 O
GPIO0_67 7 IO 0
GPMC0_A24 8 OZ 0
MCASP1_AXR2 12 IO
AB27 prg0_pru1_gpo5 PRG0_PRU1_GPO5 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 1/1
PRG0_PRU1_GPI5 1 I 0
GPIO0_68 7 IO 0
GPMC0_AD8 8 IO 0
MCASP1_ACLKX 12 IO
BOOTMODE6 Bootstrap I
AC26 prg0_pru1_gpo6 PRG0_PRU1_GPO6 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI6 1 I 0
PRG0_RGMII2_RXC 2 I 0
RGMII4_RXC 4 I 0
RMII4_TXD0 5 O
GPIO0_69 7 IO 0
GPMC0_A25 8 OZ 0
MCASP1_AXR3 12 IO
AA24 prg0_pru1_gpo7 PRG0_PRU1_GPO7 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI7 1 I 0
PRG0_IEP1_EDC_LATCH_IN1 2 I 0
SPI3_CS0 4 IO 1
MCAN11_TX 6 O
GPIO0_70 7 IO 0
GPMC0_AD9 8 IO 0
MCASP1_AXR4 12 IO
UART2_TXD 14 O
AA28 prg0_pru1_gpo8 PRG0_PRU1_GPO8 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI8 1 I 0
PRG0_PWM2_TZ_OUT 3 O
MCAN11_RX 6 I 1
GPIO0_71 7 IO 0
GPMC0_AD10 8 IO 0
MCASP1_AFSX 12 IO
Y24 prg0_pru1_gpo9 PRG0_PRU1_GPO9 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI9 1 I 0
PRG0_UART0_RXD 2 I 1
SPI3_CS3 4 IO 1
PRG0_IEP0_EDIO_DATA_IN_OUT30 6 IO 0
GPIO0_72 7 IO 0
GPMC0_AD11 8 IO 0
DSS_FSYNC3 10 O
MCASP1_AXR5 12 IO
UART8_RXD 14 I
AA25 prg0_pru1_gpo10 PRG0_PRU1_GPO10 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI10 1 I 0
PRG0_UART0_TXD 2 O
PRG0_PWM2_TZ_IN 3 I 0
PRG0_IEP0_EDIO_DATA_IN_OUT31 6 IO 0
GPIO0_73 7 IO 0
GPMC0_AD12 8 IO 0
CLKOUT 9 OZ 0
MCASP1_AXR6 12 IO
UART8_TXD 14 O
AG26 prg0_pru1_gpo11 PRG0_PRU1_GPO11 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI11 1 I 0
PRG0_RGMII2_TD0 2 O
RGMII4_TD0 4 O
RMII4_TX_EN 5 O
GPIO0_74 7 IO 0
GPMC0_A26 8 OZ 0
MCASP1_AXR7 12 IO
AF27 prg0_pru1_gpo12 PRG0_PRU1_GPO12 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI12 1 I 0
PRG0_RGMII2_TD1 2 O
PRG0_PWM1_A0 3 IO 0
RGMII4_TD1 4 O
GPIO0_75 7 IO 0
MCASP1_AXR8 12 IO
UART8_CTSn 14 I
AF26 prg0_pru1_gpo13 PRG0_PRU1_GPO13 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI13 1 I 0
PRG0_RGMII2_TD2 2 O
PRG0_PWM1_B0 3 IO 1
RGMII4_TD2 4 O
GPIO0_76 7 IO 0
MCASP1_AXR9 12 IO
UART8_RTSn 14 O
AE25 prg0_pru1_gpo14 PRG0_PRU1_GPO14 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI14 1 I 0
PRG0_RGMII2_TD3 2 O
PRG0_PWM1_A1 3 IO 0
RGMII4_TD3 4 O
GPIO0_77 7 IO 0
MCASP2_AXR0 12 IO
UART2_CTSn 14 I
AF29 prg0_pru1_gpo15 PRG0_PRU1_GPO15 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI15 1 I 0
PRG0_RGMII2_TX_CTL 2 O
PRG0_PWM1_B1 3 IO 1
RGMII4_TX_CTL 4 O
GPIO0_78 7 IO 0
MCASP2_AXR1 12 IO
UART2_RTSn 14 O
AG29 prg0_pru1_gpo16 PRG0_PRU1_GPO16 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI16 1 I 0
PRG0_RGMII2_TXC 2 IO 0
PRG0_PWM1_A2 3 IO 0
RGMII4_TXC 4 O 0
GPIO0_79 7 IO 0
MCASP2_AXR2 12 IO
Y25 prg0_pru1_gpo17 PRG0_PRU1_GPO17 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 1/1
PRG0_PRU1_GPI17 1 I 0
PRG0_IEP1_EDC_SYNC_OUT1 2 O
PRG0_PWM1_B2 3 IO 1
SPI3_CLK 4 IO 0
GPIO0_80 7 IO 0
GPMC0_AD13 8 IO 0
MCASP2_AXR3 12 IO
BOOTMODE3 Bootstrap I
AA26 prg0_pru1_gpo18 PRG0_PRU1_GPO18 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI18 1 I 0
PRG0_IEP1_EDC_LATCH_IN0 2 I 0
PRG0_PWM1_TZ_IN 3 I 0
SPI3_D0 4 IO 0
MCAN12_TX 6 O
GPIO0_81 7 IO 0
GPMC0_AD14 8 IO 0
MCASP2_AFSX 12 IO
UART2_RXD 14 I
AA29 prg0_pru1_gpo19 PRG0_PRU1_GPO19 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU1_GPI19 1 I 0
PRG0_IEP1_EDC_SYNC_OUT0 2 O
PRG0_PWM1_TZ_OUT 3 O
SPI3_D1 4 IO 0
MCAN12_RX 6 I 1
GPIO0_82 7 IO 0
GPMC0_AD15 8 IO 0
MCASP2_ACLKX 12 IO
AD18 prg1_mdio0_mdc PRG1_MDIO0_MDC 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0/1
SPI1_CS3 1 IO 1
I2C4_SDA 2 IOD 1
RMII_REF_CLK 5 I 0
GPIO0_42 7 IO 0
VPFE0_DATA12 11 I
MCASP5_AXR3 12 IO 0
MCASP5_AFSR 13 IO 0
UART3_RTSn 14 O 0
AD19 prg1_mdio0_mdio PRG1_MDIO0_MDIO 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
SPI1_CS2 1 IO 1
I2C4_SCL 2 IOD 1
GPIO0_41 7 IO 0
DSS_FSYNC1 10 O
VPFE0_DATA11 11 I
MCASP5_AXR2 12 IO 0
MCASP5_ACLKR 13 IO 0
UART3_CTSn 14 I 0
AC23 prg1_pru0_gpo0 PRG1_PRU0_GPO0 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI0 1 I 0
PRG1_RGMII1_RD0 2 I 0
PRG1_PWM3_A0 3 IO 0
RGMII1_RD0 4 I 0
RMII1_RXD0 5 I 0
GPIO0_1 7 IO 0
GPMC0_BE1n 8 O 0
RGMII7_RD0 9 I
MCASP6_ACLKX 12 IO
UART0_RXD 14 I
AG22 prg1_pru0_gpo1 PRG1_PRU0_GPO1 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI1 1 I 0
PRG1_RGMII1_RD1 2 I 0
PRG1_PWM3_B0 3 IO 1
RGMII1_RD1 4 I 0
RMII1_RXD1 5 I 0
GPIO0_2 7 IO 0
GPMC0_WAIT0 8 I 0
RGMII7_RD1 9 I 0
MCASP6_AFSX 12 IO
UART0_TXD 14 O
AF22 prg1_pru0_gpo2 PRG1_PRU0_GPO2 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI2 1 I 0
PRG1_RGMII1_RD2 2 I 0
PRG1_PWM2_A0 3 IO 0
RGMII1_RD2 4 I 0
RMII1_CRS_DV 5 I 0
GPIO0_3 7 IO 0
GPMC0_WAIT1 8 I 0
RGMII7_RD2 9 I 0
MCASP6_AXR0 12 IO
UART1_RXD 14 I
AJ23 prg1_pru0_gpo3 PRG1_PRU0_GPO3 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI3 1 I 0
PRG1_RGMII1_RD3 2 I 0
PRG1_PWM3_A2 3 IO 0
RGMII1_RD3 4 I 0
RMII1_RX_ER 5 I 0
GPIO0_4 7 IO 0
GPMC0_DIR 8 O 0
RGMII7_RD3 9 I
MCASP6_AXR1 12 IO
UART1_TXD 14 O
AH23 prg1_pru0_gpo4 PRG1_PRU0_GPO4 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI4 1 I 0
PRG1_RGMII1_RX_CTL 2 I 0
PRG1_PWM2_B0 3 IO 1
RGMII1_RX_CTL 4 I 0
RMII1_TXD0 5 O
GPIO0_5 7 IO 0
GPMC0_CSn2 8 O 0
RGMII7_RX_CTL 9 I
MCASP6_AXR2 12 IO
MCASP6_ACLKR 13 IO 0
UART2_RXD 14 I 0
AD20 prg1_pru0_gpo5 PRG1_PRU0_GPO5 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 1/1
PRG1_PRU0_GPI5 1 I 0
PRG1_PWM3_B2 3 IO 1
RMII1_TX_EN 5 O
GPIO0_6 7 IO 0
GPMC0_WEn 8 O 0
MCASP3_AXR0 12 IO
BOOTMODE0 Bootstrap I
AD22 prg1_pru0_gpo6 PRG1_PRU0_GPO6 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI6 1 I 0
PRG1_RGMII1_RXC 2 I 0
PRG1_PWM3_A1 3 IO 0
RGMII1_RXC 4 I 0
RMII1_TXD1 5 O
AUDIO_EXT_REFCLK0 6 IO 0
GPIO0_7 7 IO 0
GPMC0_CSn3 8 O 0
RGMII7_RXC 9 I
MCASP6_AXR3 12 IO
MCASP6_AFSR 13 IO 0
UART2_TXD 14 O 0
AE20 prg1_pru0_gpo7 PRG1_PRU0_GPO7 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI7 1 I 0
PRG1_IEP0_EDC_LATCH_IN1 2 I 0
PRG1_PWM3_B1 3 IO 1
AUDIO_EXT_REFCLK1 5 IO 0
MCAN4_TX 6 O
GPIO0_8 7 IO 0
MCASP3_AXR1 12 IO
AJ20 prg1_pru0_gpo8 PRG1_PRU0_GPO8 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI8 1 I 0
PRG1_PWM2_A1 3 IO 0
RMII5_RXD0 5 I 0
MCAN4_RX 6 I 1
GPIO0_9 7 IO 0
GPMC0_OEn_REn 8 O 0
VOUT0_DATA22 10 O
MCASP3_AXR2 12 IO
AG20 prg1_pru0_gpo9 PRG1_PRU0_GPO9 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI9 1 I 0
PRG1_UART0_CTSn 2 I 1
PRG1_PWM3_TZ_IN 3 I 0
SPI6_CS1 4 IO 1
RMII5_RXD1 5 I 0
GPIO0_10 7 IO 0
GPMC0_ADVn_ALE 8 O 0
PRG1_IEP0_EDIO_DATA_IN_OUT28 9 IO
VOUT0_DATA23 10 O 0
MCASP3_ACLKX 12 IO
AD21 prg1_pru0_gpo10 PRG1_PRU0_GPO10 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI10 1 I 0
PRG1_UART0_RTSn 2 O
PRG1_PWM2_B1 3 IO 1
SPI6_CS2 4 IO 1
RMII5_CRS_DV 5 I 0
GPIO0_11 7 IO 0
GPMC0_BE0n_CLE 8 O 0
PRG1_IEP0_EDIO_DATA_IN_OUT29 9 IO
OBSCLK2 10 O 0
MCASP3_AFSX 12 IO
AF24 prg1_pru0_gpo11 PRG1_PRU0_GPO11 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI11 1 I 0
PRG1_RGMII1_TD0 2 O
PRG1_PWM3_TZ_OUT 3 O
RGMII1_TD0 4 O
MCAN4_TX 6 O
GPIO0_12 7 IO 0
RGMII7_TD0 9 O
VOUT0_DATA16 10 O
VPFE0_DATA0 11 I
MCASP7_ACLKX 12 IO 0
AJ24 prg1_pru0_gpo12 PRG1_PRU0_GPO12 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI12 1 I 0
PRG1_RGMII1_TD1 2 O
PRG1_PWM0_A0 3 IO 0
RGMII1_TD1 4 O
MCAN4_RX 6 I 1
GPIO0_13 7 IO 0
RGMII7_TD1 9 O
VOUT0_DATA17 10 O
VPFE0_DATA1 11 I
MCASP7_AFSX 12 IO 0
AG24 prg1_pru0_gpo13 PRG1_PRU0_GPO13 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI13 1 I 0
PRG1_RGMII1_TD2 2 O
PRG1_PWM0_B0 3 IO 1
RGMII1_TD2 4 O
MCAN5_TX 6 O
GPIO0_14 7 IO 0
RGMII7_TD2 9 O
VOUT0_DATA18 10 O
VPFE0_DATA2 11 I
MCASP7_AXR0 12 IO 0
AD24 prg1_pru0_gpo14 PRG1_PRU0_GPO14 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI14 1 I 0
PRG1_RGMII1_TD3 2 O
PRG1_PWM0_A1 3 IO 0
RGMII1_TD3 4 O
MCAN5_RX 6 I 1
GPIO0_15 7 IO 0
RGMII7_TD3 9 O
VOUT0_DATA19 10 O
VPFE0_DATA3 11 I
MCASP7_AXR1 12 IO 0
AC24 prg1_pru0_gpo15 PRG1_PRU0_GPO15 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI15 1 I 0
PRG1_RGMII1_TX_CTL 2 O
PRG1_PWM0_B1 3 IO 1
RGMII1_TX_CTL 4 O
MCAN6_TX 6 O
GPIO0_16 7 IO 0
RGMII7_TX_CTL 9 O
VOUT0_DATA20 10 O
VPFE0_DATA4 11 I
MCASP7_AXR2 12 IO 0
MCASP7_ACLKR 13 IO 0
AE24 prg1_pru0_gpo16 PRG1_PRU0_GPO16 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI16 1 I 0
PRG1_RGMII1_TXC 2 IO 0
PRG1_PWM0_A2 3 IO 0
RGMII1_TXC 4 O 0
MCAN6_RX 6 I 1
GPIO0_17 7 IO 0
RGMII7_TXC 9 O
VOUT0_DATA21 10 O 0
VPFE0_DATA5 11 I
MCASP7_AXR3 12 IO 0
MCASP7_AFSR 13 IO 0
AJ21 prg1_pru0_gpo17 PRG1_PRU0_GPO17 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI17 1 I 0
PRG1_IEP0_EDC_SYNC_OUT1 2 O
PRG1_PWM0_B2 3 IO 1
RMII5_TXD1 5 O
MCAN5_TX 6 O
GPIO0_18 7 IO 0
VPFE0_DATA6 11 I
MCASP3_AXR3 12 IO 0
AE21 prg1_pru0_gpo18 PRG1_PRU0_GPO18 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI18 1 I 0
PRG1_IEP0_EDC_LATCH_IN0 2 I 0
PRG1_PWM0_TZ_IN 3 I 0
RMII5_RX_ER 5 I 0
MCAN5_RX 6 I 1
GPIO0_19 7 IO 0
VPFE0_DATA7 11 I
MCASP4_ACLKX 12 IO 0
AH21 prg1_pru0_gpo19 PRG1_PRU0_GPO19 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU0_GPI19 1 I 0
PRG1_IEP0_EDC_SYNC_OUT0 2 O
PRG1_PWM0_TZ_OUT 3 O
RMII5_TXD0 5 O
MCAN6_TX 6 O
GPIO0_20 7 IO 0
VOUT0_EXTPCLKIN 10 I
VPFE0_PCLK 11 I 0
MCASP4_AFSX 12 IO 0
AE22 prg1_pru1_gpo0 PRG1_PRU1_GPO0 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI0 1 I 0
PRG1_RGMII2_RD0 2 I 0
RGMII2_RD0 4 I 0
RMII2_RXD0 5 I 0
GPIO0_21 7 IO 0
RGMII8_RD0 8 I 0
VOUT0_DATA0 10 O
VPFE0_HD 11 I
MCASP8_ACLKX 12 IO 0
AG23 prg1_pru1_gpo1 PRG1_PRU1_GPO1 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI1 1 I 0
PRG1_RGMII2_RD1 2 I 0
RGMII2_RD1 4 I 0
RMII2_RXD1 5 I 0
GPIO0_22 7 IO 0
RGMII8_RD1 8 I 0
VOUT0_DATA1 10 O
VPFE0_FIELD 11 I
MCASP8_AFSX 12 IO 0
AF23 prg1_pru1_gpo2 PRG1_PRU1_GPO2 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI2 1 I 0
PRG1_RGMII2_RD2 2 I 0
PRG1_PWM2_A2 3 IO 0
RGMII2_RD2 4 I 0
RMII2_CRS_DV 5 I 0
GPIO0_23 7 IO 0
RGMII8_RD2 8 I 0
VOUT0_DATA2 10 O
VPFE0_VD 11 I
MCASP8_AXR0 12 IO 0
MCASP3_ACLKR 13 IO 0
AD23 prg1_pru1_gpo3 PRG1_PRU1_GPO3 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI3 1 I 0
PRG1_RGMII2_RD3 2 I 0
RGMII2_RD3 4 I 0
RMII2_RX_ER 5 I 0
GPIO0_24 7 IO 0
RGMII8_RD3 8 I 0
EQEP1_A 9 I 0
VOUT0_DATA3 10 O 0
VPFE0_WEN 11 I
MCASP8_AXR1 12 IO 0
MCASP3_AFSR 13 IO 0
TIMER_IO2 14 IO 0
AH24 prg1_pru1_gpo4 PRG1_PRU1_GPO4 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI4 1 I 0
PRG1_RGMII2_RX_CTL 2 I 0
PRG1_PWM2_B2 3 IO 1
RGMII2_RX_CTL 4 I 0
RMII2_TXD0 5 O
GPIO0_25 7 IO 0
RGMII8_RX_CTL 8 I 0
EQEP1_B 9 I 0
VOUT0_DATA4 10 O 0
VPFE0_DATA13 11 I
MCASP8_AXR2 12 IO 0
MCASP8_ACLKR 13 IO 0
TIMER_IO3 14 IO 0
AG21 prg1_pru1_gpo5 PRG1_PRU1_GPO5 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI5 1 I 0
RMII5_TX_EN 5 O
MCAN6_RX 6 I 1
GPIO0_26 7 IO 0
GPMC0_WPn 8 O 0
EQEP1_S 9 IO
VOUT0_DATA5 10 O 0
MCASP4_AXR0 12 IO
TIMER_IO4 14 IO
AE23 prg1_pru1_gpo6 PRG1_PRU1_GPO6 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI6 1 I 0
PRG1_RGMII2_RXC 2 I 0
RGMII2_RXC 4 I 0
RMII2_TXD1 5 O
GPIO0_27 7 IO 0
RGMII8_RXC 8 I 0
VOUT0_DATA6 10 O
VPFE0_DATA14 11 I
MCASP8_AXR3 12 IO 0
MCASP8_AFSR 13 IO 0
TIMER_IO5 14 IO 0
AC21 prg1_pru1_gpo7 PRG1_PRU1_GPO7 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI7 1 I 0
PRG1_IEP1_EDC_LATCH_IN1 2 I 0
SPI6_CS0 4 IO 1
RMII6_RX_ER 5 I 0
MCAN7_TX 6 O
GPIO0_28 7 IO 0
VOUT0_DATA7 10 O
VPFE0_DATA15 11 I
MCASP4_AXR1 12 IO 0
UART3_TXD 14 O
Y23 prg1_pru1_gpo8 PRG1_PRU1_GPO8 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI8 1 I 0
PRG1_PWM2_TZ_OUT 3 O
RMII6_RXD0 5 I 0
MCAN7_RX 6 I 1
GPIO0_29 7 IO 0
GPMC0_CSn1 8 O 0
VOUT0_DATA8 10 O
MCASP4_AXR2 12 IO
UART3_RXD 14 I
AF21 prg1_pru1_gpo9 PRG1_PRU1_GPO9 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI9 1 I 0
PRG1_UART0_RXD 2 I 1
SPI6_CS3 4 IO 1
RMII6_RXD1 5 I 0
MCAN8_TX 6 O
GPIO0_30 7 IO 0
GPMC0_CSn0 8 O 0
PRG1_IEP0_EDIO_DATA_IN_OUT30 9 IO
VOUT0_DATA9 10 O 0
MCASP4_AXR3 12 IO
AB23 prg1_pru1_gpo10 PRG1_PRU1_GPO10 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI10 1 I 0
PRG1_UART0_TXD 2 O
PRG1_PWM2_TZ_IN 3 I 0
RMII6_CRS_DV 5 I 0
MCAN8_RX 6 I 1
GPIO0_31 7 IO 0
GPMC0_CLKOUT 8 O 0
PRG1_IEP0_EDIO_DATA_IN_OUT31 9 IO
VOUT0_DATA10 10 O 0
GPMC0_FCLK_MUX 11 O
MCASP5_ACLKX 12 IO
AJ25 prg1_pru1_gpo11 PRG1_PRU1_GPO11 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI11 1 I 0
PRG1_RGMII2_TD0 2 O
RGMII2_TD0 4 O
RMII2_TX_EN 5 O
GPIO0_32 7 IO 0
RGMII8_TD0 8 O 0
EQEP1_I 9 IO
VOUT0_DATA11 10 O 0
MCASP9_ACLKX 12 IO
AH25 prg1_pru1_gpo12 PRG1_PRU1_GPO12 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI12 1 I 0
PRG1_RGMII2_TD1 2 O
PRG1_PWM1_A0 3 IO 0
RGMII2_TD1 4 O
MCAN7_TX 6 O
GPIO0_33 7 IO 0
RGMII8_TD1 8 O 0
VOUT0_DATA12 10 O
MCASP9_AFSX 12 IO
AG25 prg1_pru1_gpo13 PRG1_PRU1_GPO13 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI13 1 I 0
PRG1_RGMII2_TD2 2 O
PRG1_PWM1_B0 3 IO 1
RGMII2_TD2 4 O
MCAN7_RX 6 I 1
GPIO0_34 7 IO 0
RGMII8_TD2 8 O 0
VOUT0_DATA13 10 O
VPFE0_DATA8 11 I
MCASP9_AXR0 12 IO 0
MCASP4_ACLKR 13 IO 0
AH26 prg1_pru1_gpo14 PRG1_PRU1_GPO14 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI14 1 I 0
PRG1_RGMII2_TD3 2 O
PRG1_PWM1_A1 3 IO 0
RGMII2_TD3 4 O
MCAN8_TX 6 O
GPIO0_35 7 IO 0
RGMII8_TD3 8 O 0
VOUT0_DATA14 10 O
MCASP9_AXR1 12 IO
MCASP4_AFSR 13 IO 0
AJ27 prg1_pru1_gpo15 PRG1_PRU1_GPO15 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI15 1 I 0
PRG1_RGMII2_TX_CTL 2 O
PRG1_PWM1_B1 3 IO 1
RGMII2_TX_CTL 4 O
MCAN8_RX 6 I 1
GPIO0_36 7 IO 0
RGMII8_TX_CTL 8 O 0
VOUT0_DATA15 10 O
VPFE0_DATA9 11 I
MCASP9_AXR2 12 IO 0
MCASP9_ACLKR 13 IO 0
AJ26 prg1_pru1_gpo16 PRG1_PRU1_GPO16 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI16 1 I 0
PRG1_RGMII2_TXC 2 IO 0
PRG1_PWM1_A2 3 IO 0
RGMII2_TXC 4 O 0
GPIO0_37 7 IO 0
RGMII8_TXC 8 O 0
VOUT0_VP2_HSYNC 9 O 0
VOUT0_HSYNC 10 O
MCASP9_AXR3 12 IO
MCASP9_AFSR 13 IO 0
VOUT0_VP0_HSYNC 14 O 0
AC22 prg1_pru1_gpo17 PRG1_PRU1_GPO17 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 1/1
PRG1_PRU1_GPI17 1 I 0
PRG1_IEP1_EDC_SYNC_OUT1 2 O
PRG1_PWM1_B2 3 IO 1
SPI6_CLK 4 IO 0
RMII6_TX_EN 5 O
PRG1_ECAP0_SYNC_OUT 6 O
GPIO0_38 7 IO 0
VOUT0_VP2_DE 9 O
VOUT0_DE 10 O
VPFE0_DATA10 11 I
MCASP5_AFSX 12 IO 0
VOUT0_VP0_DE 14 O
BOOTMODE1 Bootstrap I
AJ22 prg1_pru1_gpo18 PRG1_PRU1_GPO18 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI18 1 I 0
PRG1_IEP1_EDC_LATCH_IN0 2 I 0
PRG1_PWM1_TZ_IN 3 I 0
SPI6_D0 4 IO 0
RMII6_TXD0 5 O
PRG1_ECAP0_SYNC_IN 6 I 0
GPIO0_39 7 IO 0
VOUT0_VP2_VSYNC 9 O
VOUT0_VSYNC 10 O
MCASP5_AXR0 12 IO
VOUT0_VP0_VSYNC 14 O
AH22 prg1_pru1_gpo19 PRG1_PRU1_GPO19 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1
PRG1_PRU1_GPI19 1 I 0
PRG1_IEP1_EDC_SYNC_OUT0 2 O
PRG1_PWM1_TZ_OUT 3 O
SPI6_D1 4 IO 0
RMII6_TXD1 5 O
PRG1_ECAP0_IN_APWM_OUT 6 IO 0
GPIO0_40 7 IO 0
VOUT0_PCLK 10 O
MCASP5_AXR1 12 IO
T6 resetstatz RESETSTATz 0 O OFF 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/0
C28 RESET_REQZ RESET_REQz 0 I PU 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1/1
U25 rgmii5_rxc RGMII5_RXC 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1
I2C6_SDA 2 IOD 1
VOUT1_DATA7 4 O
TRC_DATA5 5 O
EHRPWM_TZn_IN1 6 I 0
GPIO0_92 7 IO 0
GPMC0_A8 8 OZ 0
MCASP10_AXR3 12 IO
EHRPWM_SOCA 14 O
U26 rgmii5_rx_ctl RGMII5_RX_CTL 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1
RMII7_RX_ER 1 I 0
I2C2_SDA 2 IOD 1
VOUT1_DATA1 4 O
TRC_CTL 5 O
EHRPWM0_SYNCO 6 O
GPIO0_86 7 IO 0
GPMC0_A2 8 OZ 0
MCASP10_AFSX 12 IO
U29 rgmii5_txc RGMII5_TXC 0 O OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1
RMII7_TX_EN 1 O
I2C6_SCL 2 IOD 1
VOUT1_DATA6 4 O
TRC_DATA4 5 O
EHRPWM1_B 6 IO 0
GPIO0_91 7 IO 0
GPMC0_A7 8 OZ 0
MCASP10_AXR2 12 IO
U23 rgmii5_tx_ctl RGMII5_TX_CTL 0 O OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0/1
RMII7_CRS_DV 1 I 0
I2C2_SCL 2 IOD 1
VOUT1_DATA0 4 O
TRC_CLK 5 O
EHRPWM0_SYNCI 6 I 0
GPIO0_85 7 IO 0
GPMC0_A1 8 OZ 0
MCASP10_ACLKX 12 IO
W26 rgmii6_rxc RGMII6_RXC 0 I OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1
AUDIO_EXT_REFCLK2 3 IO 0
VOUT1_DE 4 O
TRC_DATA17 5 O
EHRPWM4_B 6 IO 0
GPIO0_104 7 IO 0
GPMC0_A20 8 OZ 0
VOUT1_VP0_DE 9 O
MCASP10_AXR7 12 IO
V23 rgmii6_rx_ctl RGMII6_RX_CTL 0 I OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1
RMII8_RX_ER 1 I 0
VOUT1_DATA13 4 O
TRC_DATA11 5 O
EHRPWM3_A 6 IO 0
GPIO0_98 7 IO 0
GPMC0_A14 8 OZ 0
MCASP10_AFSR 12 IO
W29 rgmii6_txc RGMII6_TXC 0 O OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1
RMII8_TX_EN 1 O
SPI5_CLK 3 IO 0
VOUT1_PCLK 4 O
TRC_DATA16 5 O
EHRPWM4_A 6 IO 0
GPIO0_103 7 IO 0
GPMC0_A19 8 OZ 0
MCASP10_AXR6 12 IO
Y28 rgmii6_tx_ctl RGMII6_TX_CTL 0 O OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0/1
RMII8_CRS_DV 1 I 0
VOUT1_DATA12 4 O
TRC_DATA10 5 O
GPIO0_97 7 IO 0
GPMC0_A13 8 OZ 0
MCASP10_ACLKR 12 IO
T23 rgmii5_rd0 RGMII5_RD0 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1
RMII7_RXD0 1 I 0
UART6_RTSn 3 O
VOUT1_DATA11 4 O
TRC_DATA9 5 O
GPIO0_96 7 IO 0
GPMC0_A12 8 OZ 0
MCASP11_AXR3 12 IO
R23 rgmii5_rd1 RGMII5_RD1 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1
RMII7_RXD1 1 I 0
UART6_CTSn 3 I 1
VOUT1_DATA10 4 O
TRC_DATA8 5 O
EHRPWM_TZn_IN2 6 I 0
GPIO0_95 7 IO 0
GPMC0_A11 8 OZ 0
MCASP11_AXR2 12 IO
EHRPWM_SOCB 14 O
U24 rgmii5_rd2 RGMII5_RD2 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1
UART3_RTSn 1 O
UART6_TXD 3 O
VOUT1_DATA9 4 O
TRC_DATA7 5 O
EHRPWM2_B 6 IO 0
GPIO0_94 7 IO 0
GPMC0_A10 8 OZ 0
MCASP11_AXR1 12 IO
U27 rgmii5_rd3 RGMII5_RD3 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1
UART3_CTSn 1 I 1
UART6_RXD 3 I 1
VOUT1_DATA8 4 O
TRC_DATA6 5 O
EHRPWM2_A 6 IO 0
GPIO0_93 7 IO 0
GPMC0_A9 8 OZ 0
MCASP11_AXR0 12 IO
U28 rgmii5_td0 RGMII5_TD0 0 O OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0/1
RMII7_TXD0 1 O
I2C3_SDA 2 IOD 1
VOUT1_DATA5 4 O
TRC_DATA3 5 O
EHRPWM1_A 6 IO 0
GPIO0_90 7 IO 0
GPMC0_A6 8 OZ 0
MCASP11_AFSX 12 IO
V27 rgmii5_td1 RGMII5_TD1 0 O OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0/1
RMII7_TXD1 1 O
I2C3_SCL 2 IOD 1
VOUT1_DATA4 4 O
TRC_DATA2 5 O
EHRPWM0_B 6 IO 0
GPIO0_89 7 IO 0
GPMC0_A5 8 OZ 0
MCASP11_ACLKX 12 IO
V29 rgmii5_td2 RGMII5_TD2 0 O OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0/1
UART3_TXD 1 O
SYNC3_OUT 3 O
VOUT1_DATA3 4 O
TRC_DATA1 5 O
EHRPWM0_A 6 IO 0
GPIO0_88 7 IO 0
GPMC0_A4 8 OZ 0
MCASP10_AXR1 12 IO
V28 rgmii5_td3 RGMII5_TD3 0 O OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0/1
UART3_RXD 1 I 1
SYNC2_OUT 3 O
VOUT1_DATA2 4 O
TRC_DATA0 5 O
EHRPWM_TZn_IN0 6 I 0
GPIO0_87 7 IO 0
GPMC0_A3 8 OZ 0
MCASP10_AXR0 12 IO
W25 rgmii6_rd0 RGMII6_RD0 0 I OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1
RMII8_RXD0 1 I 0
SPI5_CS1 3 IO 1
AUDIO_EXT_REFCLK3 4 IO 0
TRC_DATA21 5 O
EHRPWM_TZn_IN5 6 I 0
GPIO0_108 7 IO 0
GPMC0_DIR 8 O 0
MCASP11_AXR7 12 IO
W24 rgmii6_rd1 RGMII6_RD1 0 I OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1
RMII8_RXD1 1 I 0
SPI5_D1 3 IO 0
VOUT1_EXTPCLKIN 4 I 0
TRC_DATA20 5 O
EHRPWM5_B 6 IO 0
GPIO0_107 7 IO 0
GPMC0_BE1n 8 O 0
MCASP11_AXR6 12 IO
Y27 rgmii6_rd2 RGMII6_RD2 0 I OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1
UART4_RTSn 1 O
UART5_TXD 3 O
TRC_DATA19 5 O
EHRPWM5_A 6 IO 0
GPIO0_106 7 IO 0
GPMC0_A22 8 OZ 0
MCASP11_AXR5 12 IO
Y29 rgmii6_rd3 RGMII6_RD3 0 I OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1
UART4_CTSn 1 I 1
UART5_RXD 3 I 1
CLKOUT 4 OZ
TRC_DATA18 5 O
EHRPWM_TZn_IN4 6 I 0
GPIO0_105 7 IO 0
GPMC0_A21 8 OZ 0
MCASP11_AXR4 12 IO
W27 rgmii6_td0 RGMII6_TD0 0 O OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0/1
RMII8_TXD0 1 O
SPI5_CS0 3 IO 1
VOUT1_HSYNC 4 O
TRC_DATA15 5 O
EHRPWM_TZn_IN3 6 I 0
GPIO0_102 7 IO 0
GPMC0_A18 8 OZ 0
VOUT1_VP0_HSYNC 9 O
MCASP10_AXR5 12 IO
V25 rgmii6_td1 RGMII6_TD1 0 O OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0/1
RMII8_TXD1 1 O
SPI5_D0 3 IO 0
VOUT1_VSYNC 4 O
TRC_DATA14 5 O
EHRPWM3_SYNCO 6 O
GPIO0_101 7 IO 0
GPMC0_A17 8 OZ 0
VOUT1_VP0_VSYNC 9 O
MCASP10_AXR4 12 IO
W28 rgmii6_td2 RGMII6_TD2 0 O OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0/1
UART4_TXD 1 O
SPI5_CS2 3 IO 1
VOUT1_DATA15 4 O
TRC_DATA13 5 O
EHRPWM3_SYNCI 6 I 0
GPIO0_100 7 IO 0
GPMC0_A16 8 OZ 0
MCASP11_AFSR 12 IO
W23 rgmii6_td3 RGMII6_TD3 0 O OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0/1
UART4_RXD 1 I 1
SPI5_CS3 3 IO 1
VOUT1_DATA14 4 O
TRC_DATA12 5 O
EHRPWM3_B 6 IO 0
GPIO0_99 7 IO 0
GPMC0_A15 8 OZ 0
MCASP11_ACLKR 12 IO
E7 SERDES4_REFCLK_N SERDES4_REFCLK_N IO OFF 0.8 V  VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
AE18 serdes0_rext SERDES0_REXT A OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
AE13 serdes1_rext SERDES1_REXT A OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
AD13 serdes2_rext SERDES2_REXT A OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
F9 serdes4_rext SERDES4_REXT I OFF 0.8 V  VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
E8 SERDES4_REFCLK_P SERDES4_REFCLK_P IO OFF 0.8 V  VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
AE8 serdes3_rext SERDES3_REXT A OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
AH19 SERDES0_RX0_N SERDES0_RX0_N I OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
SGMII1_RXN0 I
PCIE0_RXN0 I
USB0_SSRX2N I
AJ18 SERDES0_RX0_P SERDES0_RX0_P I OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
SGMII1_RXP0 I
PCIE0_RXP0 I
USB0_SSRX2P I
AH18 SERDES0_RX1_N SERDES0_RX1_N I OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
SGMII2_RXN0 I
PCIE0_RXN1 I
USB0_SSRX1N I
AJ17 SERDES0_RX1_P SERDES0_RX1_P I OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
SGMII2_RXP0 I
PCIE0_RXP1 I
USB0_SSRX1P I
AF19 SERDES0_TX0_N SERDES0_TX0_N O OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
SGMII1_TXN0 O
PCIE0_TXN0 O
USB0_SSTX2N O
AG18 SERDES0_TX0_P SERDES0_TX0_P O OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
SGMII1_TXP0 O
PCIE0_TXP0 O
USB0_SSTX2P O
AF18 SERDES0_TX1_N SERDES0_TX1_N O OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
SGMII2_TXN0 O
PCIE0_TXN1 O
USB0_SSTX1N O
AG17 SERDES0_TX1_P SERDES0_TX1_P O OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
SGMII2_TXP0 O
PCIE0_TXP1 O
USB0_SSTX1P O
AH15 SERDES1_RX0_N SERDES1_RX0_N I OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
SGMII3_RXN0 I
PCIE1_RXN0 I
USB1_SSRX2N I
PRG1_SGMII0_RXN0 I
AJ14 SERDES1_RX0_P SERDES1_RX0_P I OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
SGMII3_RXP0 I
PCIE1_RXP0 I
USB1_SSRX2P I
PRG1_SGMII0_RXP0 I
AH16 SERDES1_RX1_N SERDES1_RX1_N I OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
SGMII4_RXN0 I
PCIE1_RXN1 I
USB1_SSRX1N I
PRG1_SGMII1_RXN0 I
AJ15 SERDES1_RX1_P SERDES1_RX1_P I OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
SGMII4_RXP0 I
PCIE1_RXP1 I
USB1_SSRX1P I
PRG1_SGMII1_RXP0 I
AF15 SERDES1_TX0_N SERDES1_TX0_N O OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
SGMII3_TXN0 O
PCIE1_TXN0 O
USB1_SSTX2N O
PRG1_SGMII0_TXN0 O
AG14 SERDES1_TX0_P SERDES1_TX0_P O OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
SGMII3_TXP0 O
PCIE1_TXP0 O
USB1_SSTX2P O
PRG1_SGMII0_TXP0 O
AF16 SERDES1_TX1_N SERDES1_TX1_N O OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
SGMII4_TXN0 O
PCIE1_TXN1 O
USB1_SSTX1N O
PRG1_SGMII1_TXN0 O
AG15 SERDES1_TX1_P SERDES1_TX1_P O OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
SGMII4_TXP0 O
PCIE1_TXP1 O
USB1_SSTX1P O
PRG1_SGMII1_TXP0 O
AH13 SERDES2_RX0_N SERDES2_RX0_N I OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
PCIE2_RXN0 I
USB1_SSRX2N I
PRG1_SGMII0_RXN0
AJ12 SERDES2_RX0_P SERDES2_RX0_P I OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
PCIE2_RXP0 I
USB1_SSRX2P I
PRG1_SGMII0_RXP0
AH12 SERDES2_RX1_N SERDES2_RX1_N I OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
PCIE2_RXN1 I
USB1_SSRX1N I
PRG1_SGMII1_RXN0
AJ11 SERDES2_RX1_P SERDES2_RX1_P I OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
PCIE2_RXP1 I
USB1_SSRX1P I
PRG1_SGMII1_RXP0
AF13 SERDES2_TX0_N SERDES2_TX0_N O OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
PCIE2_TXN0 O
USB1_SSTX2N O
PRG1_SGMII0_TXN0
AG12 SERDES2_TX0_P SERDES2_TX0_P O OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
PCIE2_TXP0 O
USB1_SSTX2P O
PRG1_SGMII0_TXP0
AF12 SERDES2_TX1_N SERDES2_TX1_N O OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
PCIE2_TXN1 O
USB1_SSTX1N O
PRG1_SGMII1_TXN0
AG11 SERDES2_TX1_P SERDES2_TX1_P O OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
PCIE2_TXP1 O
USB1_SSTX1P O
PRG1_SGMII1_TXP0
AH9 SERDES3_RX0_N SERDES3_RX0_N I OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
PCIE3_RXN0 I
USB0_SSRX2N I
AJ8 SERDES3_RX0_P SERDES3_RX0_P I OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
PCIE3_RXP0 I
USB0_SSRX2P I
AH10 SERDES3_RX1_N SERDES3_RX1_N I OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
PCIE3_RXN1 I
USB0_SSRX1N I
AJ9 SERDES3_RX1_P SERDES3_RX1_P I OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
PCIE3_RXP1 I
USB0_SSRX1P I
AF9 SERDES3_TX0_N SERDES3_TX0_N O OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
PCIE3_TXN0 O
USB0_SSTX2N O
AG8 SERDES3_TX0_P SERDES3_TX0_P O OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
PCIE3_TXP0 O
USB0_SSTX2P O
AF10 SERDES3_TX1_N SERDES3_TX1_N O OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
PCIE3_TXN1 O
USB0_SSTX1N O
AG9 SERDES3_TX1_P SERDES3_TX1_P O OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
PCIE3_TXP1 O
USB0_SSTX1P O
D9 SERDES4_RX0_N SERDES4_RX0_N I OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
SGMII5_RXN0 I
C10 SERDES4_RX0_P SERDES4_RX0_P I OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
SGMII5_RXP0 I
D8 SERDES4_RX1_N SERDES4_RX1_N I OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
SGMII6_RXN0 I
C9 SERDES4_RX1_P SERDES4_RX1_P I OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
SGMII6_RXP0 I
D6 SERDES4_RX2_N SERDES4_RX2_N I OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
SGMII7_RXN0 I
C7 SERDES4_RX2_P SERDES4_RX2_P I OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
SGMII7_RXP0 I
D5 SERDES4_RX3_N SERDES4_RX3_N I OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
SGMII8_RXN0 I
C6 SERDES4_RX3_P SERDES4_RX3_P I OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
SGMII8_RXP0 I
B11 SERDES4_TX0_N SERDES4_TX0_N O OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
DP0_TX0_N O
SGMII5_TXN0 O
A12 SERDES4_TX0_P SERDES4_TX0_P O OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
DP0_TX0_P O
SGMII5_TXP0 O
B10 SERDES4_TX1_N SERDES4_TX1_N O OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
DP0_TX1_N O
SGMII6_TXN0 O
A11 SERDES4_TX1_P SERDES4_TX1_P O OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
DP0_TX1_P O
SGMII6_TXP0 O
B8 SERDES4_TX2_N SERDES4_TX2_N O OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
DP0_TX2_N O
SGMII7_TXN0 O
A9 SERDES4_TX2_P SERDES4_TX2_P O OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
DP0_TX2_P O
SGMII7_TXP0 O
B7 SERDES4_TX3_N SERDES4_TX3_N O OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
DP0_TX3_N O
SGMII8_TXN0 O
A8 SERDES4_TX3_P SERDES4_TX3_P O OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP 4-L-PHY
DP0_TX3_P O
SGMII8_TXP0 O
U4 soc_safety_errorn SOC_SAFETY_ERRORn 0 IO PD 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1/0
AA1 spi0_clk SPI0_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1
UART1_CTSn 1 I 1
I2C2_SCL 2 IOD 1
GPIO0_113 7 IO 0
Y1 spi1_clk SPI1_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1
UART5_CTSn 1 I 1
I2C4_SDA 2 IOD 1
UART2_RXD 3 I 1
GPIO0_118 7 IO 0
PRG0_IEP0_EDC_SYNC_OUT0 8 O 0
AA2 spi0_cs0 SPI0_CS0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1
UART0_RTSn 1 O
GPIO0_111 7 IO 0
Y4 spi0_cs1 SPI0_CS1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1
CPTS0_TS_COMP 1 O
I2C3_SCL 2 IOD 1
DP0_HPD 5 I 0
PRG1_IEP0_EDIO_OUTVALID 6 O
GPIO0_112 7 IO 0
AB5 spi0_d0 SPI0_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1
UART1_RTSn 1 O
I2C2_SDA 2 IOD 1
GPIO0_114 7 IO 0
AA3 spi0_d1 SPI0_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1
I2C6_SCL 2 IOD 1
GPIO0_115 7 IO 0
Y3 spi1_cs0 SPI1_CS0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1
UART0_CTSn 1 I 1
UART5_RXD 3 I 1
PRG0_IEP0_EDIO_OUTVALID 6 O
GPIO0_116 7 IO 0
PRG0_IEP0_EDC_LATCH_IN0 8 I 0
W4 spi1_cs1 SPI1_CS1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1
CPTS0_TS_SYNC 1 O
I2C3_SDA 2 IOD 1
UART5_TXD 3 O
GPIO0_117 7 IO 0
Y5 spi1_d0 SPI1_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1
UART5_RTSn 1 O
I2C4_SCL 2 IOD 1
UART2_TXD 3 O
GPIO0_119 7 IO 0
PRG0_IEP1_EDC_LATCH_IN0 8 I 0
Y2 spi1_d1 SPI1_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1
I2C6_SDA 2 IOD 1
GPIO0_120 7 IO 0
PRG0_IEP1_EDC_SYNC_OUT0 8 O 0
E29 tck TCK 0 I PU 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1/1
V1 tdi TDI 0 I PU 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1/1
V3 tdo TDO 0 OZ PU 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/0
V6 timer_io0 TIMER_IO0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 1/1
ECAP1_IN_APWM_OUT 1 IO 0
SYSCLKOUT0 2 O
SPI7_D0 6 IO 0
GPIO1_13 7 IO 0
BOOTMODE4 Bootstrap I
V5 timer_io1 TIMER_IO1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 1/1
ECAP2_IN_APWM_OUT 1 IO 0
OBSCLK0 2 O
SPI7_D1 6 IO 0
GPIO1_14 7 IO 0
BOOTMODE5 Bootstrap I
V2 tms TMS 0 I PU 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1/1
F24 trstn TRSTn 0 I PD 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1/1
AC2 uart0_ctsn UART0_CTSn 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1
TIMER_IO6 1 IO 0
SPI0_CS2 2 IO 1
MCAN2_RX 3 I 1
SPI2_CS0 4 IO 1
EQEP0_A 5 I 0
GPIO0_123 7 IO 0
MLB0_MLBSIG 8 IO 0
AB1 uart0_rtsn UART0_RTSn 0 O OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1
TIMER_IO7 1 IO 0
SPI0_CS3 2 IO 1
MCAN2_TX 3 O
SPI2_CLK 4 IO 0
EQEP0_B 5 I 0
GPIO0_124 7 IO 0
AB2 uart0_rxd UART0_RXD 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1
SPI2_CS1 4 IO 1
GPIO0_121 7 IO 0
AB3 uart0_txd UART0_TXD 0 O OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1
SPI2_CS2 4 IO 1
SPI7_CS1 6 IO 1
GPIO0_122 7 IO 0
AC4 uart1_ctsn UART1_CTSn 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1
MCAN3_RX 1 I 1
SPI2_D0 4 IO 0
EQEP0_S 5 IO 0
GPIO0_127 7 IO 0
MLB0_MLBCLK 8 I 0
AD5 uart1_rtsn UART1_RTSn 0 O OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1
MCAN3_TX 1 O
SPI2_D1 4 IO 0
EQEP0_I 5 IO 0
GPIO1_0 7 IO 0
MLB0_MLBDAT 8 IO 0
AA4 uart1_rxd UART1_RXD 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1
SPI7_CS2 6 IO 1
GPIO0_125 7 IO 0
AB4 uart1_txd UART1_TXD 0 O OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1
I3C0_SDAPULLEN 5 O
SPI7_CS3 6 IO 1
GPIO0_126 7 IO 0
AE6 ufs0_ref_clk UFS0_REF_CLK O OFF 0.8 V  VDDA_0P8_UFS / VDDA_1P8_UFS M-PHY
AD6 ufs0_rstn UFS0_RSTn O OFF 0.8 V  VDDA_0P8_UFS / VDDA_1P8_UFS M-PHY
AH3 ufs0_rx_dn0 UFS0_RX_DN0 I OFF 0.8 V  VDDA_0P8_UFS / VDDA_1P8_UFS M-PHY
AH4 ufs0_rx_dn1 UFS0_RX_DN1 I OFF 0.8 V  VDDA_0P8_UFS / VDDA_1P8_UFS M-PHY
AJ2 ufs0_rx_dp0 UFS0_RX_DP0 I OFF 0.8 V  VDDA_0P8_UFS / VDDA_1P8_UFS M-PHY
AJ3 ufs0_rx_dp1 UFS0_RX_DP1 I OFF 0.8 V  VDDA_0P8_UFS / VDDA_1P8_UFS M-PHY
AG6 ufs0_tx_dn0 UFS0_TX_DN0 O OFF 0.8 V  VDDA_0P8_UFS / VDDA_1P8_UFS M-PHY
AG5 ufs0_tx_dn1 UFS0_TX_DN1 O OFF 0.8 V  VDDA_0P8_UFS / VDDA_1P8_UFS M-PHY
AF7 ufs0_tx_dp0 UFS0_TX_DP0 O OFF 0.8 V  VDDA_0P8_UFS / VDDA_1P8_UFS M-PHY
AF6 ufs0_tx_dp1 UFS0_TX_DP1 O OFF 0.8 V  VDDA_0P8_UFS / VDDA_1P8_UFS M-PHY
AJ5 usb0_dm USB0_DM IO OFF 3.3 V  VDDA_0P8_USB / VDDA_1P8_USB / VDDA_3P3_USB USB2PHY
AH6 usb0_dp USB0_DP IO OFF 3.3 V  VDDA_0P8_USB / VDDA_1P8_USB / VDDA_3P3_USB USB2PHY
U6 usb0_drvvbus USB0_DRVVBUS 0 O PD 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1
USB1_DRVVBUS 1 O
GPIO1_29 7 IO 0
AC6 usb0_id USB0_ID A OFF 3.3 V  VDDA_0P8_USB / VDDA_1P8_USB / VDDA_3P3_USB USB2PHY
AB6 usb0_rcalib USB0_RCALIB IO OFF 3.3 V  VDDA_0P8_USB / VDDA_1P8_USB / VDDA_3P3_USB USB2PHY
AC7 usb0_vbus USB0_VBUS A OFF 3.3 V  VDDA_0P8_USB / VDDA_1P8_USB / VDDA_3P3_USB USB2PHY
AH7 usb1_dm USB1_DM IO OFF 3.3 V   VDDA_0P8_USB / VDDA_1P8_USB / VDDA_3P3_USB USB2PHY
AJ6 usb1_dp USB1_DP IO OFF 3.3 V   VDDA_0P8_USB / VDDA_1P8_USB / VDDA_3P3_USB USB2PHY
AD7 usb1_id USB1_ID A OFF 3.3 V   VDDA_0P8_USB / VDDA_1P8_USB / VDDA_3P3_USB USB2PHY
AD9 usb1_rcalib USB1_RCALIB IO OFF 3.3 V   VDDA_0P8_USB / VDDA_1P8_USB / VDDA_3P3_USB USB2PHY
AD8 usb1_vbus USB1_VBUS A OFF 3.3 V   VDDA_0P8_USB / VDDA_1P8_USB / VDDA_3P3_USB USB2PHY
L14, V13, V16, W19 VDDAR_CORE VDDAR_CORE PWR
L11, W12 VDDAR_CPU VDDAR_CPU PWR
K19, T19 vddar_mcu vddar_mcu PWR
H17 VDDA_0P8_CSIRX VDDA_0P8_CSIRX PWR
G12, J12 VDDA_0P8_DP VDDA_0P8_DP PWR
G14, H13 VDDA_0P8_DP_C VDDA_0P8_DP_C PWR
H15 VDDA_0P8_DSITX VDDA_0P8_DSITX PWR
J16 VDDA_0P8_DSITX_C VDDA_0P8_DSITX_C PWR
AB9 VDDA_0P8_UFS VDDA_0P8_UFS PWR
AA10 VDDA_0P8_USB VDDA_0P8_USB PWR
AA15, Y14, Y16 VDDA_0P8_SERDES0_1 VDDA_0P8_SERDES0_1 PWR
AA12, Y11, Y13 VDDA_0P8_SERDES2_3 VDDA_0P8_SERDES2_3 PWR
AB14, AB15 VDDA_0P8_SERDES_C0_1 VDDA_0P8_SERDES_C0_1 PWR
AB12, AB13 VDDA_0P8_SERDES_C2_3 VDDA_0P8_SERDES_C2_3 PWR
G16 VDDA_1P8_CSIRX VDDA_1P8_CSIRX PWR
H11 VDDA_1P8_DP VDDA_1P8_DP PWR
J14 VDDA_1P8_DSITX VDDA_1P8_DSITX PWR
AC8 VDDA_1P8_UFS VDDA_1P8_UFS PWR
AC9 vdda_1p8_usb vdda_1p8_usb PWR
AC14, AC15 VDDA_1P8_SERDES0_1 VDDA_1P8_SERDES0_1 PWR
AC11, AC12 VDDA_1P8_SERDES2_3 VDDA_1P8_SERDES2_3 PWR
AB10 vdda_3p3_usb vdda_3p3_usb PWR
N22 VDDA_ADC0 VDDA_ADC0 PWR
M23 VDDA_ADC1 VDDA_ADC1 PWR
N9 VDDA_0P8_PLL_DDR VDDA_0P8_PLL_DDR PWR
G18 VDDA_MCU_PLLGRP0 VDDA_MCU_PLLGRP0 PWR
P21 VDDA_MCU_TEMP VDDA_MCU_TEMP PWR
W7 VDDA_1P8_MLB VDDA_1P8_MLB PWR
Y20 VDDA_PLLGRP0 VDDA_PLLGRP0 PWR
W17 VDDA_PLLGRP1 VDDA_PLLGRP1 PWR
M17 VDDA_PLLGRP2 VDDA_PLLGRP2 PWR
L12 VDDA_PLLGRP3 VDDA_PLLGRP3 PWR
R11 VDDA_PLLGRP4 VDDA_PLLGRP4 PWR
P9 VDDA_PLLGRP5 VDDA_PLLGRP5 PWR
W18 VDDA_PLLGRP6 VDDA_PLLGRP6 PWR
W8 VDDA_0P8_PLL_MLB VDDA_0P8_PLL_MLB PWR
P22 vdda_por_wkup vdda_por_wkup PWR
W15 VDDA_TEMP0_1 VDDA_TEMP0_1 PWR
H9 VDDA_TEMP2_3 VDDA_TEMP2_3 PWR
M26 VMON_ER_VSYS VMON_ER_VSYS A
V19 VMON_IR_VEXT VMON_IR_VEXT A
H22 VDDA_WKUP VDDA_WKUP PWR
U8, V7 VDDSHV0 VDDSHV0 PWR
L22, M22 VDDSHV0_MCU VDDSHV0_MCU PWR
AA19, AA20, AC19, AC20 VDDSHV1 VDDSHV1 PWR
H19, H21, J20 VDDSHV1_MCU VDDSHV1_MCU PWR
AA17, AB16, AB18, AC17 VDDSHV2 VDDSHV2 PWR
J22, K21 VDDSHV2_MCU VDDSHV2_MCU PWR
V21, W22 VDDSHV3 VDDSHV3 PWR
AA21, Y22 VDDSHV4 VDDSHV4 PWR
T20, T22 VDDSHV5 VDDSHV5 PWR
U20, U22 VDDSHV6 VDDSHV6 PWR
A1, G8, J8, K7, L8, M7, N8, P7, R8, T1 vdds_ddr vdds_ddr PWR
H7, J6, R6, T7 vdds_ddr_bias vdds_ddr_bias PWR
M9 VDDS_DDR_C VDDS_DDR_C PWR
AA8, AB7, Y7 vdds_mmc0 vdds_mmc0 PWR
R21 VDDS_OSC1 VDDS_OSC1 PWR
J10, K11, K13, K15, K17, K9, L10, L16, L18, M15, N14, N16, N18, P13, P15, P17, R14, R16, R18, R20, T15, T17, T9, U14, U16, U18, V15, V17, V20, W14 VDD_CORE VDD_CORE PWR
N10, P11, R10, R12, U10, V11, V9, W10 VDD_CPU VDD_CPU PWR
Y9 VDDA_0P8_DLL_MMC0 VDDA_0P8_DLL_MMC0 PWR
L20, M19, M21, N20, P19 vdd_mcu vdd_mcu PWR
AB11 vpp_core vpp_core PWR
F17 VPP_MCU VPP_MCU PWR
AA13, AC10, AC13, AD11, AD14, AD17, AE10, AE12, AE15, AE16, AE19, AE7, AF20, AF25, AF5, AG4, AG7, AH2, AH20, AH5, AJ4, AJ7, B3, B6, C1, C5, D2, D4, E1, E5, F4, G1, G7, H4, H6, K1, K4, L3, M1, M28, M4, M6, N27, N29, N3, P1, P28, P4, R3, U5 vss vss GND
A10, A13, A16, A19, A22, A7, AA11, AA14, AA16, AA18, AA7, AA9, AB17, AB19, AB20, AB22, AB8, AC16, AF11, AF14, AF17, AF8, AG10, AG13, AG16, AG19, AH11, AH14, AH17, AH8, AJ10, AJ13, AJ16, AJ19, B12, B15, B18, B21, B9, C11, C14, C17, C20, C8, D10, D13, D16, D19, D7, E12, E15, E9, F14, F8, G11, G13, G15, G17, H10, H12, H14, H16, H18, H20, H8, J11, J13, J15, J17, J21, J23, J7, J9, K10, K12, K14, K16, K18, K20, K22, K8, L13, L15, L17, L19, L21, L23, L7, L9, M10, M14, M16, M18, M20, M8, N15, N17, N19, N21, N7, P10, P12, P14, P16, P18, P20, P8, R13, R15, R17, R19, R7, R9, T10, T14, T16, T18, T21, T8, U15, U17, U19, U21, U9, V10, V12, V14, V18, V8, W11, W13, W16, W20, W9, Y10, Y12, Y15, Y17, Y19, Y21, Y8 VSS VSS GND
F26 wkup_gpio0_0 MCU_SPI1_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 1/1
MCU_SPI1_CLK 1 IO 0
WKUP_GPIO0_0 7 IO 0
MCU_BOOTMODE03 Bootstrap I
F25 wkup_gpio0_1 MCU_SPI1_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 1/1
MCU_SPI1_D0 1 IO 0
WKUP_GPIO0_1 7 IO 0
MCU_BOOTMODE04 Bootstrap I
F28 wkup_gpio0_2 MCU_SPI1_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 1/1
MCU_SPI1_D1 1 IO 0
WKUP_GPIO0_2 7 IO 0
MCU_BOOTMODE05 Bootstrap I
F27 wkup_gpio0_3 MCU_SPI1_CS0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 0/1
MCU_SPI1_CS0 1 IO 1
WKUP_GPIO0_3 7 IO 0
G25 wkup_gpio0_4 MCU_MCAN1_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0/1
MCU_MCAN1_TX 1 O
MCU_SPI0_CS3 2 IO 1
MCU_ADC_EXT_TRIGGER0 3 I pad
WKUP_GPIO0_4 7 IO 0
G24 wkup_gpio0_5 MCU_MCAN1_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 0/1
MCU_MCAN1_RX 1 I 1
MCU_SPI1_CS3 2 IO 1
MCU_ADC_EXT_TRIGGER1 3 I pad
WKUP_GPIO0_5 7 IO 0
F29 wkup_gpio0_6 WKUP_UART0_CTSn 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 0/1
WKUP_UART0_CTSn 1 I 1
MCU_CPTS0_HW1TSPUSH 2 I 0
MCU_I2C1_SCL 3 IOD 1
WKUP_GPIO0_6 7 IO 0
G28 wkup_gpio0_7 WKUP_UART0_RTSn 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0/1
WKUP_UART0_RTSn 1 O
MCU_CPTS0_HW2TSPUSH 2 I 0
MCU_I2C1_SDA 3 IOD 1
WKUP_GPIO0_7 7 IO 0
G27 wkup_gpio0_8 MCU_I2C1_SCL 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 0/1
MCU_I2C1_SCL 1 IOD 1
MCU_CPTS0_TS_SYNC 2 O
MCU_I3C1_SCL 3 IO 1
MCU_TIMER_IO6 4 IO 0
WKUP_GPIO0_8 7 IO 0
G26 wkup_gpio0_9 MCU_I2C1_SDA 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 0/1
MCU_I2C1_SDA 1 IOD 1
MCU_CPTS0_TS_COMP 2 O
MCU_I3C1_SDA 3 IO 1
MCU_TIMER_IO7 4 IO 0
WKUP_GPIO0_9 7 IO 0
H26 wkup_gpio0_10 MCU_EXT_REFCLK0 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 0/1
MCU_EXT_REFCLK0 1 I 0
MCU_UART0_TXD 2 O
MCU_ADC_EXT_TRIGGER0 3 I 0
MCU_CPTS0_RFT_CLK 4 I 0
MCU_SYSCLKOUT0 5 O
WKUP_GPIO0_10 7 IO 0
H27 wkup_gpio0_11 MCU_OBSCLK0 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0/1
MCU_OBSCLK0 1 O
MCU_UART0_RXD 2 I 1
MCU_ADC_EXT_TRIGGER1 3 I 0
MCU_TIMER_IO1 4 IO 0
MCU_I3C1_SDAPULLEN 5 O
MCU_CLKOUT0 6 OZ
WKUP_GPIO0_11 7 IO 0
G29 wkup_gpio0_12 MCU_UART0_TXD 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1/1
MCU_SPI0_CS1 1 O
WKUP_GPIO0_12 7 IO 0
MCU_BOOTMODE08 Bootstrap I
H28 wkup_gpio0_13 MCU_UART0_RXD 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 1/1
MCU_SPI1_CS1 1 O
WKUP_GPIO0_13 7 IO 0
MCU_BOOTMODE09 Bootstrap I
H29 wkup_gpio0_14 MCU_UART0_CTSn 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 1/1
MCU_SPI0_CS2 1 O
WKUP_GPIO0_14 7 IO 0
MCU_BOOTMODE06 Bootstrap I
J27 wkup_gpio0_15 MCU_UART0_RTSn 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1/1
MCU_SPI1_CS2 1 O
WKUP_GPIO0_15 7 IO 0
MCU_BOOTMODE07 Bootstrap I
J25 wkup_i2c0_scl WKUP_I2C0_SCL 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes I2C OD FS 1 1/0
WKUP_GPIO0_62 7 IO 0
H24 wkup_i2c0_sda WKUP_I2C0_SDA 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes I2C OD FS 1 1/0
WKUP_GPIO0_63 7 IO 0
N28 wkup_lfosc0_xi WKUP_LFOSC0_XI I OFF 1.8 V VDDA_WKUP LFOSC
N26 wkup_lfosc0_xo WKUP_LFOSC0_XO O OFF 1.8 V VDDA_WKUP LFOSC
M29 wkup_osc0_xi WKUP_OSC0_XI I OFF 1.8 V VDDA_WKUP HFOSC
M27 wkup_osc0_xo WKUP_OSC0_XO O OFF 1.8 V VDDA_WKUP HFOSC
J29 wkup_uart0_rxd WKUP_UART0_RXD 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 0/1
WKUP_GPIO0_56 7 IO 0
J28 wkup_uart0_txd WKUP_UART0_TXD 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0/1
WKUP_GPIO0_57 7 IO 0
  1. The MUXMODE field is not used to select the multiplexed signal function for this pin. For more information, see ADC Integration Details section in Device Configuration chapter of the device TRM.

The following list describes the table column headers:

  1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
  2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
  3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).
    Note:

    Table 5-1, Pin Attributes, does not take into account the subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 5.3, Signal Descriptions.

  4. MUXMODE: Multiplexing mode number:
    1. MUXMODE 0 is the primary muxmode. The primary muxmode is not necessarily the default muxmode.
      Note:

      The default muxmode is the mode at the release of the reset; also see the BALL RESET REL. MUXMODE column.

    2. MUXMODE 1 through 7 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used.
    3. MCU_BOOTMODE pins are latched on the rising edge of MCU_PORz_OUT. BOOTMODE pins are latched on the rising edge of PORz_OUT.
    4. An empty box means Not Applicable.
  5. TYPE: Signal type and direction:
    • I = Input
    • O = Output
    • IO = Input or Output
    • IOD = Open drain terminal - Input or Output
    • IOZ = Input, Output or Three-state terminal
    • OZ = Output or Three-state terminal
    • A = Analog
    • PWR = Power
    • GND = Ground
    • CAP = LDO Capacitor.
  6. BALL RESET STATE: The state of the terminal at power-on reset:
    • DRIVE 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
    • DRIVE 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
    • OFF: High-impedance
    • PD: High-impedance with an active pulldown resistor
    • PU: High-impedance with an active pullup resistor
    • An empty box means Not Applicable.
  7. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal.
    An empty box means Not Applicable.
  8. I/O VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply).
    An empty box means Not Applicable.
  9. POWER: The voltage supply that powers the terminal IO buffers.
    An empty box means Not Applicable.
  10. HYS: Indicates if the input buffer has hysteresis:
    • Yes: With hysteresis
    • No: Without hysteresis

      An empty box means No.

    For more information, see the hysteresis values in, Electrical Characteristics.

  11. BUFFER TYPE: This column describes the associated output buffer type

    An empty box means Not Applicable.

    For drive strength of the associated output buffer, refer to, Electrical Characteristics.

  12. PULL UP/DOWN TYPE: Indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
    • PU: Internal pullup
    • PD: Internal pulldown
    • PU/PD: Internal pullup and pulldown
    • An empty box means No pull.
  13. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0", logic "1", or "PIN" level) when the peripheral pin function is not selected by any of the PINCNTLx registers.
    • 0: Logic 0 driven on the input signal port of the peripheral.
    • 1: Logic 1 driven on the input signal port of the peripheral.
    • An empty box means Not Applicable.
  14. RXACTIVE / TXDISABLE: This column indicates the default value of the RXACTIVE / TXDISABLE bits in the PADCONFIG register.
    • RXACTIVE: 0 = receiver disabled, 1 = receiver enabled.
    • TXDISABLE: 0 = driver enabled, 1 = driver disabled.
    • An empty box means Not Applicable.
    Note:

    Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration (HiZ mode is not an input signal).

    Note:

    When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided.