JAJSN65A October   2019  – October 2021 DRV10982-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Regulators
        1. 8.3.1.1 Step-Down Regulator
        2. 8.3.1.2 3.3-V and 1.8-V LDO
      2. 8.3.2 Protection Circuits
        1. 8.3.2.1 Thermal Shutdown
        2. 8.3.2.2 Undervoltage Lockout (UVLO)
        3. 8.3.2.3 Overcurrent Protection
        4. 8.3.2.4 Lock
      3. 8.3.3 Motor Speed Control
      4. 8.3.4 Load Dump Handling
      5. 8.3.5 Sleep or Standby Condition
        1. 8.3.5.1 Required Sequence to Enter Sleep Mode
          1. 8.3.5.1.1 Option 1
          2. 8.3.5.1.2 Option 2
      6. 8.3.6 EEPROM Access
    4. 8.4 Device Functional Modes
      1. 8.4.1  Motor Parameters
        1. 8.4.1.1 Motor Phase Resistance
        2. 8.4.1.2 BEMF Constant
      2. 8.4.2  Starting the Motor Under Different Initial Conditions
        1. 8.4.2.1 Case 1 – Motor is Stationary
        2. 8.4.2.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 8.4.2.3 Case 3 – Motor is Spinning in the Reverse Direction
      3. 8.4.3  Motor Start Sequence
        1. 8.4.3.1 Initial Speed Detect
        2. 8.4.3.2 Motor Resynchronization
        3. 8.4.3.3 Reverse Drive
        4. 8.4.3.4 Motor Brake
        5. 8.4.3.5 Motor Initialization
          1. 8.4.3.5.1 Align
          2. 8.4.3.5.2 Initial Position Detect (IPD)
            1. 8.4.3.5.2.1 IPD Operation
            2. 8.4.3.5.2.2 IPD Release Mode
            3. 8.4.3.5.2.3 IPD Advance Angle
          3. 8.4.3.5.3 Motor Start
        6. 8.4.3.6 Start-Up Timing
      4. 8.4.4  Align Current
      5. 8.4.5  Start-Up Current Setting
        1. 8.4.5.1 Start-Up Current Ramp-Up
      6. 8.4.6  Closed Loop
        1. 8.4.6.1 Half-Cycle Control and Full-Cycle Control
        2. 8.4.6.2 Analog-Mode Speed Control
        3. 8.4.6.3 Digital PWM-Input-Mode Speed Control
        4. 8.4.6.4 I2C-Mode Speed Control
        5. 8.4.6.5 Closed-Loop Accelerate
        6. 8.4.6.6 Control Coefficient
        7. 8.4.6.7 Commutation Control Advance Angle
      7. 8.4.7  Current Limit
        1. 8.4.7.1 Acceleration Current Limit
      8. 8.4.8  Lock Detect and Fault Handling
        1. 8.4.8.1 Lock0: Lock-Detection Current Limit Triggered
        2. 8.4.8.2 Lock1: Abnormal Speed
        3. 8.4.8.3 Lock2: Abnormal Kt
        4. 8.4.8.4 Lock3 (Fault3): No-Motor Fault
        5. 8.4.8.5 Lock4: Open-Loop Motor-Stuck Lock
        6. 8.4.8.6 Lock5: Closed Loop Motor Stuck Lock
      9. 8.4.9  Anti Voltage Suppression Function
        1. 8.4.9.1 Mechanical AVS Function
        2. 8.4.9.2 Inductive AVS Function
      10. 8.4.10 PWM Output
      11. 8.4.11 FG Customized Configuration
        1. 8.4.11.1 FG Output Frequency
        2. 8.4.11.2 FG Open Loop and Lock Behavior
      12. 8.4.12 Diagnostics and Visibility
        1. 8.4.12.1 Motor-Status Readback
        2. 8.4.12.2 Motor-Speed Readback
        3. 8.4.12.3 Motor Electrical-Period Readback
        4. 8.4.12.4 BEMF Constant Read Back
        5. 8.4.12.5 Motor Estimated Position by IPD
        6. 8.4.12.6 Supply-Voltage Readback
        7. 8.4.12.7 Speed-Command Readback
        8. 8.4.12.8 Speed-Command Buffer Readback
        9. 8.4.12.9 Fault Diagnostics
    5. 8.5 Register Maps
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 Register Map
      3. 8.5.3 Register Descriptions
        1. 8.5.3.1  FaultReg Register (address = 0x00) [reset = 0x00]
        2. 8.5.3.2  MotorSpeed Register (address = 0x01) [reset = 0x00]
        3. 8.5.3.3  MotorPeriod Register (address = 0x02) [reset = 0x00]
        4. 8.5.3.4  MotorKt Register (address = 0x03) [reset = 0x00]
        5. 8.5.3.5  MotorCurrent Register (address = 0x04) [reset = 0x00]
        6. 8.5.3.6  IPDPosition–SupplyVoltage Register (address = 0x05) [reset = 0x00]
        7. 8.5.3.7  SpeedCmd–spdCmdBuffer Register (address = 0x06) [reset = 0x00]
        8. 8.5.3.8  AnalogInLvl Register (address = 0x07) [reset = 0x00]
        9. 8.5.3.9  DeviceID–RevisionID Register (address = 0x08) [reset = 0x00]
        10. 8.5.3.10 DeviceID–RevisionID Register (address = 0x08) [reset = 0x00]
        11. 8.5.3.11 Unused Registers (addresses = 0x011 Through 0x2F)
        12. 8.5.3.12 SpeedCtrl Register (address = 0x30) [reset = 0x00]
        13. 8.5.3.13 EEPROM Programming1 Register (address = 0x31) [reset = 0x00]
        14. 8.5.3.14 EEPROM Programming2 Register (address = 0x32) [reset = 0x00]
        15. 8.5.3.15 EEPROM Programming3 Register (address = 0x33) [reset = 0x00]
        16. 8.5.3.16 EEPROM Programming4 Register (address = 0x34) [reset = 0x00]
        17. 8.5.3.17 EEPROM Programming5 Register (address = 0x35) [reset = 0x00]
        18. 8.5.3.18 EEPROM Programming6 Register (address = 0x36) [reset = 0x00]
        19. 8.5.3.19 Unused Registers (addresses = 0x37 Through 0x5F)
        20. 8.5.3.20 EECTRL Register (address = 0x60) [reset = 0x00]
        21. 8.5.3.21 Unused Registers (addresses = 0x61 Through 0x8F)
        22. 8.5.3.22 CONFIG1 Register (address = 0x90) [reset = 0x00]
        23. 8.5.3.23 CONFIG2 Register (address = 0x91) [reset = 0x00]
        24. 8.5.3.24 CONFIG3 Register (address = 0x92) [reset = 0x00]
        25. 8.5.3.25 CONFIG4 Register (address = 0x93) [reset = 0x00]
        26. 8.5.3.26 CONFIG5 Register (address = 0x94) [reset = 0x00]
        27. 8.5.3.27 CONFIG6 Register (address = 0x95) [reset = 0x00]
        28. 8.5.3.28 CONFIG7 Register (address = 0x96) [reset = 0x00]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating voltage and ambient temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY CURRENT (DRV10982Q)
IVccSLEEP1Sleep currentVSPEED = 0 V; VCC = 12 V; TA = 25℃4854µA
VSPEED = 0 V; VCC = 12 V; across temperature81
IVccActive currentVSPEED > 0 V; buck regulator with inductor; no motor load1015mA
VSPEED > 0 V; buck regulator with resistor; no motor load1316
SUPPLY CURRENT (DRV10982SQ)
IVccSTBYStandby currentVSPEED = 0 V; buck regulator with
inductor		8.514mA
VSPEED = 0 V; buck regulator with
resistor		1115
IVccActive currentVSPEED > 0 V; buck regulator with
inductor; no motor load		1015mA
VSPEED > 0 V; buck regulator with
resistor; no motor load		1316
UVLO
VUVLO_RUVLO rising threshold voltage5.866.2V
VUVLO_FUVLO falling threshold voltage5.65.86V
VUVLO_HYSUVLO threshold voltage hysteresis170195220mV
VV1P8_UVLO_RV1P8 UVLO rising threshold1.51.61.7V
VV1P8_UVLO_FV1P8 UVLO falling threshold1.41.551.65V
VV3P3_UVLO_RV3P3 UVLO rising threshold2.72.852.95V
VV3P3_UVLO_FV3P3 UVLO falling threshold2.52.72.8V
VVREG_UVLO_RVREG UVLO rising threshold44.24.3V
VVREG_UVLO_FVREG UVLO falling threshold3.94.2V
LDO OUTPUT
V3P3Output voltageBuck regulator with inductor, 20-mA load3.13.33.5V
Buck regulator with resistor, no load
IV3P3_MAXMaximum load from V3P3Only with inductor mode of buck operation, with resistor mode no load20mA
V1P8Output voltageNo load1.71.81.9V
STEP-DOWN REGULATOR
VREGRegulator output voltageLSW = 47 µH, CSW = 10 µF
Iload = 100 mA		4.555.5V
RSW = 39 Ω, CSW = 10 µF
Iload = 5 mA
IREG_MAX_LMaximum load from VREG in switching modeLSW = 47 µH, CSW = 10 µF100mA
IREG_MAX_RMaximum load from VREG in linear modeRSW = 39 Ω, CSW = 10 µF5mA
INTEGRATED MOSFET
rDS(ON)Series resistance (H + L)TA = 25°C; V(VCC) > 6.5 V; Io = 1 A300400mΩ
TA = 125°C; V(VCC) > 6.5V; Io = 1 A400550
SPEED – ANALOG MODE
VAN/A_FSAnalog full-speed voltageV(V3P3) × 0.9V(V3P3)V
VAN/A_ZSAnalog zero-speed voltage0100mV
tSAMSampling period for analog voltage on SPEED pin 320µs
VAN/A_RESAnalog voltage resolution6.5mV
SPEED – PWM DIGITAL MODE
VDIG_IHPWM input high voltage2.2V
VDIG_ILPWM input low voltage0.6V
ƒPWMPWM input frequency0.1100kHz
STANDBY MODE (DRV10982SQ)
VEN_SBAnalog voltage to enter standby mode SpdCtrlMd = 0 (analog mode)100mV
VEX_SBAnalog voltage to exit standby modeSpdCtrlMd = 0 (analog mode)0.17V
tEX_SB_ANATime needed to exit from standby modeSpdCtrlMd = 0 (analog mode)
VSPEED > VEX_SB		1700ms
tEX_SB_DR_ANATime taken to drive motor after exiting standby modeSpdCtrlMd = 0 (analog mode)
VSPEED > VEX_SB; ISDen = 0; BrkDoneThr[2:0] = 0		350ms
tEX_SB_PWMTime needed to exit from standby modeSpdCtrlMd = 1 (PWM mode)
VSPEED > VDIG_IH		2µs
tEX_SB_DR_PWMTime taken to drive motor after exiting standby modeSpdCtrlMd = 1 (PWM mode)
VSPEED_DUTY > 0; ISDen = 0; BrkDoneThr[2:0] = 0		350ms
tEN_SB_ANATime needed to enter standby modeSpdCtrlMd = 0 (analog mode)
VSPEED < VEN_SB; AvSIndEn = 0		6ms
tEN_SB_PWMTime needed to enter standby modeSpdCtrlMd = 1 (PMW mode)
VSPEED < VDIG_IL; AvSIndEn = 0		60ms
SLEEP MODE (DRV10982Q)
VEN_SLAnalog voltage to enter sleep modeSpdCtrlMd = 0 (analog mode)100mV
VEX_SLAnalog voltage to exit sleep modeSpdCtrlMd = 0 (analog mode)2.2V
tEX_SL_ANATime needed to exit from sleep modeSpdCtrlMd = 0 (analog mode)
VSPEED > VEX_SL		2µs
tEX_SL_DR_ANATime taken to drive motor after exiting from sleep modeSpdCtrlMd = 0 (analog mode)
VSPEED > VEX_SL; ISDen = 0; BrkDoneThr[2:0] = 0		350ms
tEX_SL_PWMTime needed to exit from sleep modeSpdCtrlMd = 1 (PWM mode)
VSPEED > VDIG_IH		2µs
tEX_SL_DR_PWMTime taken to drive motor after exiting from sleep modeSpdCtrlMd = 1 (PWM mode)
VSPEED > VDIG_IH; ISDen = 0; BrkDoneThr[2:0] = 0		350ms
tEN_SL_ANATime needed to enter sleep modeSpdCtrlMd = 0 (analog mode)
VSPEED < VEN_SL; AvSIndEn = 0		6ms
tEN_SL_PWMTime needed to enter sleep modeSpdCtrlMd = 1 (PMW mode)
VSPEED < VDIG_IL; AvSIndEn = 0		60ms
RPD_SPEED_SLInternal SPEED pin pull down resistance to groundVSPEED = 0 (Sleep mode)55kΩ
DIGITAL I/O (DIR INPUT, FG OUTPUT )
VDIR_HInput high2.2V
VDIR_LInput low0.6V
VFG_OHOutput high voltage Io = 5 mA3.3V
VFG_OLOutput low voltage Io = 5 mA0.6V
I2C SERIAL INTERFACE
VI2C_HInput high2.2V
VI2C_LInput low0.6V
fI2CI2C clock frequency0400kHz
LOCK DETECTION RELEASE TIME
tLOCK_OFFLock release time5s
tLCK_ETRLock enter time0.3s
OVERCURRENT PROTECTION
IOC_limit_HSHS overcurrent protectionVCC < 28.5 V3.54.255.5A
IOC_limit_LSLS overcurrent protectionVCC < 28.5 V3.54.255.5A
THERMAL SHUTDOWN
TSDNJunction temperature shutdown threshold150165180°C
TSDN_HYSJunction temperature shutdown hysteresis152025°C
TWARNJunction temperature warning threshold115125140°C
PHASE DRIVER
SLPH_LH0Phase slew rate switching low to highPHslew = 0; measure 20% to 80%;
VCC = 12 V		85120145V/µs
SLPH_LH1Phase slew rate switching low to highPHslew = 1; measure 20% to 80%;
VCC = 12 V		6080100V/µs
SLPH_LH2Phase slew rate switching low to highPHslew = 2; measure 20% to 80%;
VCC = 12 V		385062V/µs
SLPH_LH3Phase slew rate switching low to highPHslew = 3; measure 20% to 80%;
VCC = 12 V		273544V/µs
SLPH_HL0Phase slew rate switching high to lowPHslew = 0; measure 80% to 20%;
VCC = 12 V		85120145V/µs
SLPH_HL1Phase slew rate switching high to lowPHslew = 1; measure 80% to 20%;
VCC = 12 V		5980100V/µs
SLPH_HL2Phase slew rate switching high to lowPHslew = 2; measure 80% to 20%;
VCC = 12 V		365060V/µs
SLPH_HL3Phase slew rate switching high to lowPHslew = 3; measure 80% to 20%;
VCC = 12 V		253545V/µs
BEMF
COMPARATOR
BEMFHYSBEMF comparator hysteresisBEMF_HYS = 072030mV
BEMF_HYS = 1174051
LOAD DUMP PROTECTION
VOV_RLoad dump protection mode entry on rising VCC threshold28.529.230V
VOV_FLoad dump protection mode exit on falling VCC threshold27.728.228.8V
VOV_HYSLoad dump protection mode hysteresis0.7311.1V
GUID-CAFC2704-868D-40FC-957A-81FF5AEB4C1F-low.gifFigure 7-1 DRV10982Q Analog Mode Timing
GUID-CCB33A63-B420-4D70-81DB-265EEBF3E472-low.gifFigure 7-2 DRV10982Q PWM Mode Timing
GUID-E22DB8C0-E593-42C4-A3F7-CB3873414A0B-low.gifFigure 7-3 DRV10982SQ Analog Mode Timing
GUID-AFCD16ED-E426-42E3-93FF-7E5A2A330692-low.gifFigure 7-4 DRV10982SQ PWM Mode Timing