SLVSB25C August   2011  – June 2015 DRV201

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Data Transmission Timing
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VCM Driver Output Stage Operation
      2. 7.3.2 Ringing Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C Bus Operation
        1. 7.5.1.1 Single Write to a Defined Location
        2. 7.5.1.2 Single Read from a Defined Location and Current Location
        3. 7.5.1.3 Sequential Read and Write
      2. 7.5.2 I2C Device Address, Start and Stop Condition
    6. 7.6 Register Maps
      1. 7.6.1 Register Address Map
      2. 7.6.2 Control Register (Control) Address - 0x02h
      3. 7.6.3 VCM MSB Current Control Register (VCM_Current_MSB) Address - 0x03h
      4. 7.6.4 VCM LSB Current Control Register (VCM_Current_LSB) Address - 0x04h
      5. 7.6.5 Status Register (Status) Address - 0x05h
      6. 7.6.6 Mode Register (Mode) Address - 0x06h
      7. 7.6.7 VCM Resonance Frequency Register (VCM_FREQ) Address - 0x07h
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 VCM Mechanical Ringing Frequency
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 User Example 1
        2. 8.2.2.2 User Example 2
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

The VBAT pin should be bypassed to GND using a low-ESR ceramic bypass capacitor with a recommended value of at least 1-µF rated for a minimum of 6.3 V. Place this capacitor as close to the VBAT and GND pins as possible with a thick trace or ground plane connection to the device GND pin.

10.2 Layout Example

DRV201 layout_ex_slvsb25.gifFigure 26. Recommended Layout Example