JAJSC15C December 2012 – March 2018 DRV2604
PRODUCTION DATA.
REG NO. | DEFAULT | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
---|---|---|---|---|---|---|---|---|---|
0x00 | 0x80 | DEVICE_ID[2:0] | ILLEGAL_ADDR | DIAG_RESULT | FB_STS | OVER_TEMP | OC_DETECT | ||
0x01 | 0x40 | DEV_RESET | STANDBY | Reserved | MODE[2:0] | ||||
0x02 | 0x00 | RTP_INPUT[7:0] | |||||||
0x03 | 0x00 | Reserved | HI_Z | Reserved | |||||
0x04 | 0x01 | WAIT1 | WAV_FRM_SEQ1[6:0] | ||||||
0x05 | 0x00 | WAIT2 | WAV_FRM_SEQ2[6:0] | ||||||
0x06 | 0x00 | WAIT3 | WAV_FRM_SEQ3[6:0] | ||||||
0x07 | 0x00 | WAIT4 | WAV_FRM_SEQ4[6:0] | ||||||
0x08 | 0x00 | WAIT5 | WAV_FRM_SEQ5[6:0] | ||||||
0x09 | 0x00 | WAIT6 | WAV_FRM_SEQ6[6:0] | ||||||
0x0A | 0x00 | WAIT7 | WAV_FRM_SEQ7[6:0] | ||||||
0x0B | 0x00 | WAIT8 | WAV_FRM_SEQ8[6:0] | ||||||
0x0C | 0x00 | Reserved | GO | ||||||
0x0D | 0x00 | ODT[7:0] | |||||||
0x0E | 0x00 | SPT[7:0] | |||||||
0x0F | 0x00 | SNT[7:0] | |||||||
0x10 | 0x00 | BRT[7:0] | |||||||
0x16 | 0x3F | RATED_VOLTAGE[7:0] | |||||||
0x17 | 0x89 | OD_CLAMP[7:0] | |||||||
0x18 | 0x0D | A_CAL_COMP[7:0] | |||||||
0x19 | 0x6D | A_CAL_BEMF[7:0] | |||||||
0x1A | 0x36 | N_ERM_LRA | FB_BRAKE_FACTOR[2:0] | LOOP_GAIN[1:0] | BEMF_GAIN[1:0] | ||||
0x1B | 0x93 | STARTUP_BOOST | Reserved | AC_COUPLE | DRIVE_TIME[4:0] | ||||
0x1C | 0xF5 | BIDIR_INPUT | BRAKE_STABILIZER | SAMPLE_TIME[1:0] | BLANKING_TIME[1:0] | IDISS_TIME[1:0] | |||
0x1D | 0x80 | NG_THRESH[1:0] | ERM_OPEN_LOOP | SUPPLY_COMP_DIS | DATA_FORMAT_RTP | LRA_DRIVE_MODE | N_PWM_ANALOG | LRA_OPEN_LOOP | |
0x1E | 0x20 | Reserved | AUTO_CAL_TIME[1:0] | Reserved | OTP_STATUS | Reserved | OTP_PROGRAM | ||
0x21 | 0x00 | VBAT[7:0] | |||||||
0x22 | 0x00 | LRA_PERIOD[7:0] | |||||||
0xFD | 0x00 | RAM_ADDR_UB[7:0] | |||||||
0xFE | 0x00 | RAM_ADDR_LB[7:0] | |||||||
0xFF | 0x00 | RAM_DATA[7:0] |