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  • DRV5033デジタル・オムニポーラ・スイッチ・ホール効果センサ

    • JAJSC01G May   2014  – September 2016 DRV5033

      PRODUCTION DATA.  

  • CONTENTS
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  • DRV5033デジタル・オムニポーラ・スイッチ・ホール効果センサ
  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Magnetic Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Field Direction Definition
      2. 7.3.2 Device Output
      3. 7.3.3 Power-On Time
      4. 7.3.4 Output Stage
      5. 7.3.5 Protection Circuits
        1. 7.3.5.1 Overcurrent Protection (OCP)
        2. 7.3.5.2 Load Dump Protection
        3. 7.3.5.3 Reverse Supply Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Standard Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Configuration Example
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Alternative Two-Wire Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デバイスの項目表記
      2. 11.1.2 デバイスのマーキング
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12メカニカル、パッケージ、および注文情報
  13. 重要なお知らせ

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • DBZ|3
    • MPDS108G
  • LPG|3
    • MPBC003B
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DATA SHEET

DRV5033デジタル・オムニポーラ・スイッチ・ホール効果センサ

このリソースの元の言語は英語です。 翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。 実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。

1 特長

  • デジタル・オムニポーラ・スイッチ・ホール・センサ
  • 優れた温度安定性
    • 温度範囲全体にわたってBOP±10%
  • 複数の感度オプション(BOP / BRP)
    • ±3.5 / ±2 mT (FA、Figure 24を参照)
    • ±6.9 / ±3.5 mT (AJ、Figure 24を参照)
  • N極とS極の磁場を検出
  • 広い範囲の電圧をサポート
    • 2.5V～38V
    • 外部レギュレータ不要
  • 広い範囲の温度で動作
    • TA = –40℃～125℃ (Q、Figure 24を参照)
  • オープン・ドレイン出力(30mAシンク)
  • 高速な電源オン時間: 35µs
  • 小さなパッケージと占有面積
    • 表面実装の3ピンSOT-23 (DBZ)
      • 2.92mm×2.37mm
    • スルーホールの3ピンTO-92 (LPG)
      • 4.00mm×3.15mm
  • 保護機能
    • 逆電圧保護(最大-22V)
    • 40Vまでの負荷ダンプをサポート
    • 出力短絡保護
    • 出力電流制限

2 アプリケーション

  • ドッキング検出
  • ドアの開閉検出
  • 近接感知
  • バルブの位置決め
  • パルスのカウント

3 概要

DRV5033デバイスはチョッパ安定化されたホール効果センサで、温度範囲全体にわたって優れた感度の安定性を持つ磁気感知ソリューションを提供し、保護機能が内蔵されています。

DRV5033は磁場方向の検出において、両方の極に対して同じように反応します。周囲の磁束密度がBOPスレッショルドを超えると、DRV5033のオープン・ドレイン出力がLOWに変化します。磁場がBRP未満に低下するまで出力はLOWに維持され、その後で出力がハイ・インピーダンスになります。出力電流シンクの容量は30mAです。2.5V～38Vまでの広い範囲の電圧で動作し、-22Vまでは逆極性保護されるため、広範な産業用アプリケーションに適したデバイスです。

逆電圧の状態、負荷ダンプ、および出力短絡や過電流に対して、内部的な保護機能が搭載されています。

製品情報(1)

型番 パッケージ 本体サイズ(公称)
DRV5033 SOT-23 (3) 2.92mm×1.30mm
TO-92 (3) 4.00mm×3.15mm
  1. 提供されているすべてのパッケージについては、巻末の注文情報を参照してください。

出力状態

DRV5033 output_state_lis152.gif

SOT-23

DRV5033 sot_package_slis150.png

TO-92

DRV5033 sip_package_slis150.png

4 改訂履歴

Changes from F Revision (May 2016) to G Revision

  • Changed the power-on time for the FA version in the Electrical Characteristics tableGo
  • Added the Layout section Go
  • Added 「ドキュメントの更新通知を受け取る方法」セクションGo

Changes from E Revision (February 2016) to F Revision

  • Revised preliminary limits for the FA versionGo

Changes from D Revision (December 2015) to E Revision

  • Added FAデバイス・オプションGo
  • Added the typical bandwidth value to the Magnetic Characteristics tableGo

Changes from C Revision (May 2015) to D Revision

  • SOT-23パッケージの本体サイズを訂正し、SIPパッケージ名をTO-92に訂正Go
  • Added BMAX to Absolute Maximum Ratings Go
  • Removed table note from junction temperature Go
  • パッケージのテープ&リールに関するMとブランクのオプションを更新Go
  • 「コミュニティ・リソース」を追加Go

Changes from B Revision (September 2014) to C Revision

  • デバイスのステータスを量産データへ更新Go

Changes from A Revision (August 2014) to B Revision

  • Changed the maximum TJ value to 150°C Go
  • Added typical rise and fall time and removed maximum value in Switching Characteristics Go
  • Updated the Magnetic Characteristics values Go
  • Updated all Typical Characteristics graphs Go
  • Updated Equation 4 Go

Changes from * Revision (May 2014) to A Revision

  • Changed 高感度オプション: +6.9 / +2.3mT (AJ) ～ +6.9 / +3.5mT (AJ)Go
  • Changed the maximum TJ value from 175°C to 150°CGo
  • Changed MIN value for IOCP from 20 to 15 Go
  • Changed Max value for IOCP from 40 to 45 Go
  • Updated Magnetic Characteristics table. Go

5 Pin Configuration and Functions

For additional configuration information, see デバイスのマーキング and メカニカル、パッケージ、および注文情報.

DBZ Package
3-Pin SOT-23
Top View
DRV5033 po_sot_slis150.gif
LPG Package
3-Pin TO-92
Top View
DRV5033 LPG-3_Pinout_Top_View.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME DBZ LPG
GND 3 2 GND Ground pin
OUT 2 3 Output Hall sensor open-drain output. The open drain requires a resistor pullup.
VCC 1 1 PWR 2.5 to 38 V power supply. Bypass this pin to the GND pin with a 0.01-µF (minimum) ceramic capacitor rated for VCC.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Power supply voltage VCC –22(2) 40 V
Voltage ramp rate (VCC), VCC < 5 V Unlimited V/µs
Voltage ramp rate (VCC), VCC > 5 V 0 2
Output pin voltage –0.5 40 V
Output pin reverse current during reverse supply condition 0 100 mA
Magnetic flux density, BMAX Unlimited
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Ensured by design. Only tested to –20 V.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2500 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Power supply voltage 2.5 38 V
VO Output pin voltage (OUT) 0 38 V
ISINK Output pin current sink (OUT)(1) 0 30 mA
TA Operating ambient temperature –40 125 °C
(1) Power dissipation and thermal limits must be observed

6.4 Thermal Information

THERMAL METRIC(1) DRV5033 UNIT
DBZ (SOT-23) LPG (TO-92)
3 PINS 3 PINS
RθJA Junction-to-ambient thermal resistance 333.2 180 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 99.9 98.6 °C/W
RθJB Junction-to-board thermal resistance 66.9 154.9 °C/W
ψJT Junction-to-top characterization parameter 4.9 40 °C/W
ψJB Junction-to-board characterization parameter 65.2 154.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VCC)
VCC VCC operating voltage 2.5 38 V
ICC Operating supply current VCC = 2.5 to 38 V, TA = 25°C 2.7 mA
VCC = 2.5 to 38 V, TA = 125°C 3 3.6
ton Power-on time AJ version 35 50 µs
FA version 35 70
OPEN DRAIN OUTPUT (OUT)
rDS(on) FET on-resistance VCC = 3.3 V, IO = 10 mA, TA = 25°C 22 Ω
VCC = 3.3 V, IO = 10 mA, TA = 125°C 36 50
Ilkg(off) Off-state leakage current Output Hi-Z 1 µA
PROTECTION CIRCUITS
VCCR Reverse supply voltage –22 V
IOCP Overcurrent protection level OUT shorted VCC 15 30 45 mA

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPEN DRAIN OUTPUT (OUT)
td Output delay time B = BRP – 10 mT to BOP + 10 mT in 1 µs 13 25 µs
tr Output rise time (10% to 90%) R1 = 1 kΩ, CO = 50 pF, VCC = 3.3 V 200 ns
tf Output fall time (90% to 10%) R1 = 1 kΩ, CO = 50 pF, VCC = 3.3 V 31 ns

6.7 Magnetic Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT(1)
ƒBW Bandwidth(2) 20 30 kHz
DRV5033FA: ±3.5 / ±2 mT
BOP Operate point; see Figure 12 TA = –40°C to 125°C ±1.8 ±3.5 ±6.8 mT
BRP Release point; see Figure 12 ±0.5 ±2 ±4.2 mT
Bhys Hysteresis; Bhys = (BOP – BRP)(3) ±1.5 mT
BO Magnetic offset; BO = (BOP + BRP) / 2 ±2.8 mT
DRV5033AJ: ±6.9 / ±3.5 mT
BOP Operate point; see Figure 12 TA = –40°C to 125°C ±3 ±6.9 ±12 mT
BRP Release point; see Figure 12 ±1 ±3.5 ±5 mT
Bhys Hysteresis; Bhys = (BOP – BRP)(3) 3.4 mT
BO Magnetic offset; BO = (BOP + BRP) / 2 5.2 mT
(1) 1 mT = 10 Gauss
(2) Bandwidth describes the fastest changing magnetic field that can be detected and translated to the output.
(3) |BOP| is always greater than |BRP|.

6.8 Typical Characteristics

DRV5033 D009_SLIS150.gif
Figure 1. ICC vs VCC
DRV5033 D001_SLIS152.gif
TA = 25°C
Figure 3. DRV5033AJ, BOP vs VCC
DRV5033 D003_SLIS152.gif
TA = 25°C
Figure 5. DRV5033AJ, BRP vs VCC
DRV5033 D007_SLIS152.gif
TA = 25°C
Figure 7. DRV5033AJ, Hysteresis vs VCC
DRV5033 D005_SLIS152.gif
TA = 25°C
Figure 9. DRV5033AJ, Offset vs VCC
DRV5033 D010_SLIS150.gif
Figure 2. ICC vs Temperature
DRV5033 D002_SLIS152.gif
VCC = 3.3 V
Figure 4. DRV5033AJ, BOP vs Temperature
DRV5033 D004_SLIS152.gif
VCC = 3.3 V
Figure 6. DRV5033AJ, BRP vs Temperature
DRV5033 D008_SLIS152.gif
VCC = 3.3 V
Figure 8. DRV5033AJ, Hysteresis vs Temperature
DRV5033 D006_SLIS152.gif
VCC = 3.3 V
Figure 10. DRV5033AJ, Offset vs Temperature

7 Detailed Description

7.1 Overview

The DRV5033 device is a chopper-stabilized hall sensor with a digital omnipolar switch output for magnetic sensing applications. The DRV5033 device can be powered with a supply voltage between 2.5 and 38 V, and will survive –22 V reverse battery conditions continuously. Note that the DRV5033 device will not be operating when about –22 to 2.4 V is applied to VCC (with respect to GND). In addition, the device can withstand voltages up to 40 V for transient durations.

The field polarity is defined as follows: a south pole near the marked side of the package is a positive magnetic field. A north pole near the marked side of the package is a negative magnetic field.

The omnipolar configuration allows the hall sensor to respond to either a south or north pole. A strong magnetic field of either polarity will cause the output to pull low (operate point, BOP), and a weaker magnetic field will cause the output to release (release point, BRP). Hysteresis is included in between the operate and release points, so magnetic field noise will not trip the output accidentally.

An external pullup resistor is required on the OUT pin. The OUT pin can be pulled up to VCC, or to a different voltage supply. This allows for easier interfacing with controller circuits.

7.2 Functional Block Diagram

DRV5033 fbd_slis150.gif

7.3 Feature Description

7.3.1 Field Direction Definition

A positive magnetic field is defined as a south pole near the marked side of the package as shown in Figure 11.

DRV5033 field_direction_slis150.gif
N = North pole, S = South pole
Figure 11. Field Direction Definition

7.3.2 Device Output

If the device is powered on with a magnetic field strength between BRP and BOP, then the device output is indeterminate and can either be Hi-Z or Low. If the field strength is greater than BOP, then the output is pulled low. If the field strength is less than BRP, then the output is released.

DRV5033 figure_12_lis152.gif Figure 12. DRV5033—BOP > 0

7.3.3 Power-On Time

After applying VCC to the DRV5033 device, ton must elapse before the OUT pin is valid. During the power-up sequence, the output is Hi-Z. A pulse as shown in Figure 13 and Figure 14 occurs at the end of ton. This pulse can allow the host processor to determine when the DRV5033 output is valid after startup. In Case 1 (Figure 13) and Case 2 (Figure 14), the output is defined assuming a constant magnetic field B > BOP and B < BRP.

DRV5033 timing_case1_slis150.gif Figure 13. Case 1: Power On When B > BOP
DRV5033 timing_case2_slis150.gif Figure 14. Case 2: Power On When B < BRP

If the device is powered on with the magnetic field strength BRP < B < BOP, then the device output is indeterminate and can either be Hi-Z or pulled low. During the power-up sequence, the output is held Hi-Z until ton has elapsed. At the end of ton, a pulse is given on the OUT pin to indicate that ton has elapsed. After ton, if the magnetic field changes such that BOP < B, the output is released. Case 3 (Figure 15) and Case 4 (Figure 16) show examples of this behavior.

DRV5033 timing_case3_slis150.gif Figure 15. Case 3: Power On When BRP < B < BOP, Followed by B > BOP
DRV5033 timing_case4_slis150.gif Figure 16. Case 4: Power On When BRP < B < BOP, Followed by B < BRP

7.3.4 Output Stage

The DRV5033 output stage uses an open-drain NMOS, and it is rated to sink up to 30 mA of current. For proper operation, calculate the value of the pullup resistor R1 using Equation 1.

Equation 1. DRV5033 eq_01_slis150.gif

The size of R1 is a tradeoff between the OUT rise time and the current when OUT is pulled low. A lower current is generally better, however faster transitions and bandwidth require a smaller resistor for faster switching.

In addition, ensure that the value of R1 > 500 Ω to ensure the output driver can pull the OUT pin close to GND.

NOTE

Vref is not restricted to VCC. The allowable voltage range of this pin is specified in the Absolute Maximum Ratings.
DRV5033 circuit_vref_slis150.gif Figure 17.

Select a value for C2 based on the system bandwidth specifications as shown in Equation 2.

Equation 2. DRV5033 eq_02_slis150.gif

Most applications do no require this C2 filtering capacitor.

7.3.5 Protection Circuits

The DRV5033 device is fully protected against overcurrent and reverse-supply conditions.

7.3.5.1 Overcurrent Protection (OCP)

An analog current-limit circuit limits the current through the FET. The driver current is clamped to IOCP. During this clamping, the rDS(on) of the output FET is increased from the nominal value.

7.3.5.2 Load Dump Protection

The DRV5033 device operates at DC VCC conditions up to 38 V nominally, and can additionally withstand VCC = 40 V. No current-limiting series resistor is required for this protection.

7.3.5.3 Reverse Supply Protection

The DRV5033 device is protected in the event that the VCC pin and the GND pin are reversed (up to –22 V).

NOTE

In a reverse supply condition, the OUT pin reverse-current must not exceed the ratings specified in the Absolute Maximum Ratings.

Table 1.

FAULT CONDITION DEVICE DESCRIPTION RECOVERY
FET overload (OCP) ISINK ≥ IOCP Operating Output current is clamped to IOCP IO < IOCP
Load dump 38 V < VCC < 40 V Operating Device will operate for a transient duration VCC ≤ 38 V
Reverse supply –22 V < VCC < 0 V Disabled Device will survive this condition VCC ≥ 2.5 V

7.4 Device Functional Modes

The DRV5033 device is active only when VCC is between 2.5 and 38 V.

When a reverse supply condition exists, the device is inactive.

 
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