JAJSKK7 November   2021 DRV8231

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
    7. 7.7 Timing Diagrams
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 External Components
    4. 8.4 Feature Description
      1. 8.4.1 Bridge Control
      2. 8.4.2 Current Regulation
      3. 8.4.3 Protection Circuits
        1. 8.4.3.1 Overcurrent Protection (OCP)
        2. 8.4.3.2 Thermal Shutdown (TSD)
        3. 8.4.3.3 VM Undervoltage Lockout (UVLO)
    5. 8.5 Device Functional Modes
      1. 8.5.1 Active Mode
      2. 8.5.2 Low-Power Sleep Mode
      3. 8.5.3 Fault Mode
    6. 8.6 Pin Diagrams
      1. 8.6.1 Logic-Level Inputs
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Brush DC Motor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Motor Voltage
          2. 9.2.1.2.2 Motor Current
          3. 9.2.1.2.3 Sense Resistor
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Stall Detection
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Stall Detection Timing
          2. 9.2.2.2.2 Stall Threshold Selection
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Relay Driving
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Control Interface for Single-Coil Relays
          2. 9.2.3.2.2 Control Interface for Dual-Coil Relays
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Multi-Sourcing with Standard Motor Driver Pinout
    3. 9.3 Current Capability and Thermal Performance
      1. 9.3.1 Power Dissipation and Output Current Capability
      2. 9.3.2 Thermal Performance
        1. 9.3.2.1 Steady-State Thermal Performance
        2. 9.3.2.2 Transient Thermal Performance
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.2 Thermal Performance

The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions.

The data in this section was simulated using the following criteria.

HSOP (DDA package)

Table 9-5 Simulation PCB Stackup Summary for HSOP package
Layer 2-layer 4-layer
Top Layer HSOP footprint with 1- or 2-oz copper thickness. See Table 9-6 for copper area varied in simulation. Thermally connected with vias (2 vias, 1.2-mm spacing, 0.3-mm diameter, 0.025-mm copper plating) from HSOP thermal pad to bottom layer and internal ground plane (4-layer only).
Layer 2, internal ground plane N/A 1-oz copper thickness, 74.2 mm x 74.2 mm copper area, thermally connected to HSOP thermal pad through vias.
Layer 3, internal supply plane N/A 1-oz copper thickness, 74.2 mm x 74.2 mm copper area, not connected to other layers.
Bottom Layer Ground plane with 1- or 2-oz copper thickness. See Table 9-6 for copper area varied in simulation. Thermally connected to HSOP thermal pad through vias. 1- or 2-oz copper thickness. Copper area fixed at 4.90 mm × 6.00 mm in simulation. Thermally connected to HSOP thermal pad through vias.

Figure 9-18 shows an example of the simulated board for the HSOP package. Table 9-6 shows the dimensions of the board that were varied for each simulation.

Figure 9-18 HSOP PCB model top layer
Table 9-6 Dimension A for 8-pin HSOP (DDA) package
Cu area (cm2) Dimension A (mm)
0.069 Package thermal pad dimensions
2 16.40
4 22.32
8 30.64
16 42.38

WSON (DSG package)

Table 9-7 Simulation PCB Stackup Summary for WSON package
Layer 2-layer 4-layer
Top Layer WSON footprint with 1- or 2-oz copper thickness. See Table 9-8 for copper area varied in simulation. Thermally connected with vias (2 vias, 1.2-mm spacing, 0.3-mm diameter, 0.025-mm copper plating) from WSON thermal pad to bottom layer and internal ground plane (4-layer only).
Layer 2, internal ground plane N/A 1-oz copper thickness, 74.2 mm x 74.2 mm copper area, thermally connected to HSOP thermal pad through vias.
Layer 3, internal supply plane N/A 1-oz copper thickness, 74.2 mm x 74.2 mm copper area, not connected to other layers.
Bottom Layer Ground plane with 1- or 2-oz copper thickness. See Table 9-8 for copper area varied in simulation. Thermally connected to WSON thermal pad through vias. 1- or 2-oz copper thickness. Copper area fixed at 2.00 mm × 2.00 mm in simulation. Thermally connected to WSON thermal pad through vias.

Figure 9-19 shows an example of the simulated board for the WSON package. Table 9-8 shows the dimensions of the board that were varied for each simulation.

Figure 9-19 WSON PCB model top layer
Table 9-8 Dimension A for 8-pin WSON package
Cu area (mm2) Dimension A (mm)
0.015 Package thermal pad dimensions
2 15.11
4 20.98
8 29.27
16 40.99