JAJSSJ5 December 2023 DRV8234
PRODUCTION DATA
The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2.
The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below.
I2C_BC | Description |
---|---|
0b | Bridge control configured by using the EN/IN1 and PH/IN2 pins. |
1b | Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. |
The control interface is selected by the PMODE bit, as shown below.
PMODE | Control Mode |
---|---|
0b | PH/EN |
1b | PWM |
The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied.
The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through.
PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below.
nSLEEP | Enable | Phase | OUT1 | OUT2 | Description |
---|---|---|---|---|---|
0 | X | X | High-Z | High-Z | Sleep Mode (H-bridge High-Z) |
1 | 1 | 0 | L | H | Reverse (Current OUT2 → OUT1) |
1 | 1 | 1 | H | L | Forward (Current OUT1 → OUT2) |
1 | 0 | X | L | L | Brake; low-side slow decay |
Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b).
Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b).
PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below.
nSLEEP | Input1 | Input2 | OUT1 | OUT2 | Description |
---|---|---|---|---|---|
0 | X | X | High-Z | High-Z | Sleep Mode (H-bridge High-Z) |
1 | 0 | 0 | High-Z | High-Z | Coast (H-bridge High-Z) |
1 | 0 | 1 | L | H | Reverse (Current OUT2 → OUT1) |
1 | 1 | 0 | H | L | Forward (Current OUT1 → OUT2) |
1 | 1 | 1 | L | L | Brake; low-side slow decay |
Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b).
Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b).
The following timing diagram shows the timing of the inputs and outputs of the motor driver.
The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET.
The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL).