JAJSQT9A November   2023  – March 2024 DRV8242-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 HW Variant
      1. 5.1.1 VQFN (20) package
    2. 5.2 SPI Variant
      1. 5.2.1 VQFN (20) package
      2. 5.2.2 VQFN (20) package
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information VQFN-RHL package
    5. 6.5  Electrical Characteristics
    6. 6.6  Transient Thermal Impedance & Current Capability
    7. 6.7  SPI Timing Requirements
    8. 6.8  Switching Waveforms
      1. 6.8.1 Output switching transients
        1. 6.8.1.1 High-Side Recirculation
    9. 6.9  Wake-up Transients
      1. 6.9.1 HW Variant
      2. 6.9.2 SPI Variant
    10. 6.10 Fault Reaction Transients
      1. 6.10.1 Retry setting
      2. 6.10.2 Latch setting
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 HW Variant
      2. 7.2.2 SPI Variant
    3. 7.3 Feature Description
      1. 7.3.1 External Components
        1. 7.3.1.1 HW Variant
        2. 7.3.1.2 SPI Variant
      2. 7.3.2 Bridge Control
        1. 7.3.2.1 PH/EN mode
        2. 7.3.2.2 PWM mode
        3. 7.3.2.3 Register - Pin Control - SPI Variant Only
      3. 7.3.3 Device Configuration
        1. 7.3.3.1 Slew Rate (SR)
        2. 7.3.3.2 IPROPI
        3. 7.3.3.3 ITRIP Regulation
        4. 7.3.3.4 DIAG
          1. 7.3.3.4.1 HW variant
          2. 7.3.3.4.2 SPI variant
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Over Current Protection (OCP)
        2. 7.3.4.2 Over Temperature Protection (TSD)
        3. 7.3.4.3 Off-State Diagnostics (OLP)
        4. 7.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only
        5. 7.3.4.5 VM Over Voltage Monitor
        6. 7.3.4.6 VM Under Voltage Monitor
        7. 7.3.4.7 Power On Reset (POR)
        8. 7.3.4.8 Event Priority
    4. 7.4 Device Functional States
      1. 7.4.1 SLEEP State
      2. 7.4.2 STANDBY State
      3. 7.4.3 Wake-up to STANDBY State
      4. 7.4.4 ACTIVE State
      5. 7.4.5 nSLEEP Reset Pulse (HW Variant, LATCHED setting Only)
    5. 7.5 Programming - SPI Variant Only
      1. 7.5.1 SPI Interface
      2. 7.5.2 Standard Frame
      3. 7.5.3 SPI Interface for Multiple Peripherals
        1. 7.5.3.1 Daisy Chain Frame for Multiple Peripherals
  9. 8 Register Map - SPI Variant Only
    1. 8.1 User Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Load Summary
    2. 9.2 Typical Application
      1. 9.2.1 HW Variant
      2. 9.2.2 SPI Variant
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance Sizing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2 Typical Application

The figures below show the typical application schematic for driving a brushed DC motor or any inductive load in various modes. There are several optional connections shown in these schematics, which are listed as follows:

  • nSLEEP pin
    • SPI (S) variant - This pin can be tied off high in the application if SLEEP function is not needed.
    • SPI (P) variant - N/A
    • HW (H) variant - Pin control is mandatory even if SLEEP function is not needed. If configured for DIAG level 5, the controller needs to issue a reset pulse (typical: 30 μsec bounded between treset max and tsleep min) during wake-up to acknowledge wake-up or power-up. If configured for DIAG level 1, the controller does not need to issue a reset pulse.
  • DRVOFF pin
    • Both SPI (P) and SPI (S) variant - This pin can be tied off low in the application if shutoff through pin function is not needed. The equivalent register bit can be used.
  • EN/IN1 pin
    • Both SPI (P) and SPI (S) variants - This pin can be tied off low or left floating if register only control is needed.
  • PH/IN2 pin
    • Both SPI (P) and SPI (S) variants - This pin can be tied off low or left floating if register only control is needed.
  • OUT1 & OUT2 pins
    • Recommend to add PCB footprints for capacitors from OUTx to GND as well as between OUTx close to the load for EMC purposes. An optional 22 nF capacitor with sufficient voltage rating can be used between OUTx to GND to improve ESD and EMC performance.
  • IPROPI pin
    • All variants - Monitoring of this output is optional. Also IPROPI pin can be tied low if ITRIP feature & IPROPI function is not needed. Recommend to add a PCB footprint for a small capacitor (10 nF to 100 nF) if needed.
  • nFAULT pin
    • Both SPI (P) and SPI (S) variants - Monitoring of this output is optional. All diagnostic information can be read from the STATUS registers.
  • SPI input pins
    • Both SPI (P) and SPI (S) variants - Inputs (SDI, nSCS, SCLK) are compatible with 3.3 V / 5 V levels.
  • SPI SDO pin
    • SPI (S) variant - SDO tracks the nSLEEP pin voltage.
    • SPI (P) variant - SDO tracks the VDD pin voltage. To interface with a 3.3 V level controller input, a level shifter or a current limiting series resistor is recommended.
  • CONFIG pins
    • HW (H) variant - Resistor is not needed for short to GND and Hi-Z level selections
      • LVL1 and LVL3 for MODE pin
      • LVL1 and LVL6 for SR, ITRIP, DIAG pins