JAJSQT9A November   2023  – March 2024 DRV8242-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 HW Variant
      1. 5.1.1 VQFN (20) package
    2. 5.2 SPI Variant
      1. 5.2.1 VQFN (20) package
      2. 5.2.2 VQFN (20) package
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information VQFN-RHL package
    5. 6.5  Electrical Characteristics
    6. 6.6  Transient Thermal Impedance & Current Capability
    7. 6.7  SPI Timing Requirements
    8. 6.8  Switching Waveforms
      1. 6.8.1 Output switching transients
        1. 6.8.1.1 High-Side Recirculation
    9. 6.9  Wake-up Transients
      1. 6.9.1 HW Variant
      2. 6.9.2 SPI Variant
    10. 6.10 Fault Reaction Transients
      1. 6.10.1 Retry setting
      2. 6.10.2 Latch setting
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 HW Variant
      2. 7.2.2 SPI Variant
    3. 7.3 Feature Description
      1. 7.3.1 External Components
        1. 7.3.1.1 HW Variant
        2. 7.3.1.2 SPI Variant
      2. 7.3.2 Bridge Control
        1. 7.3.2.1 PH/EN mode
        2. 7.3.2.2 PWM mode
        3. 7.3.2.3 Register - Pin Control - SPI Variant Only
      3. 7.3.3 Device Configuration
        1. 7.3.3.1 Slew Rate (SR)
        2. 7.3.3.2 IPROPI
        3. 7.3.3.3 ITRIP Regulation
        4. 7.3.3.4 DIAG
          1. 7.3.3.4.1 HW variant
          2. 7.3.3.4.2 SPI variant
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Over Current Protection (OCP)
        2. 7.3.4.2 Over Temperature Protection (TSD)
        3. 7.3.4.3 Off-State Diagnostics (OLP)
        4. 7.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only
        5. 7.3.4.5 VM Over Voltage Monitor
        6. 7.3.4.6 VM Under Voltage Monitor
        7. 7.3.4.7 Power On Reset (POR)
        8. 7.3.4.8 Event Priority
    4. 7.4 Device Functional States
      1. 7.4.1 SLEEP State
      2. 7.4.2 STANDBY State
      3. 7.4.3 Wake-up to STANDBY State
      4. 7.4.4 ACTIVE State
      5. 7.4.5 nSLEEP Reset Pulse (HW Variant, LATCHED setting Only)
    5. 7.5 Programming - SPI Variant Only
      1. 7.5.1 SPI Interface
      2. 7.5.2 Standard Frame
      3. 7.5.3 SPI Interface for Multiple Peripherals
        1. 7.5.3.1 Daisy Chain Frame for Multiple Peripherals
  9. 8 Register Map - SPI Variant Only
    1. 8.1 User Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Load Summary
    2. 9.2 Typical Application
      1. 9.2.1 HW Variant
      2. 9.2.2 SPI Variant
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance Sizing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.2.2 PWM mode

In this mode, the two half-bridges are configured to operate as a full-bridge. EN/IN1 provides the PWM input in one direction, while PH/IN2 provides the PWM in the other direction. For load illustration, refer the Section 9.1.1.

Table 7-5 Control table - PWM mode
nSLEEPDRVOFFEN/IN1PH/IN2OUT1OUT2IPROPIDevice State
0XXXHi-ZHi-ZNo currentSLEEP
1100Hi-ZHi-ZNo currentSTANDBY
1110Refer Off-state diagnostics tableNo currentSTANDBY
1101No currentSTANDBY
1111No currentSTANDBY
1000HHISNS1 or ISNS2(1)ACTIVE
1001L(4)HISNS2ACTIVE
1010HL(4)ISNS1ACTIVE
1011Hi-ZHi-ZNo currentSTANDBY
(1) Current sourcing out of device (VM → OUTx → Load)
(4) If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "H" for a fixed time

For the SPI variant, by setting the PWM_EXTEND bit in the CONFIG2 register, there are additional Hi-Z states that are possible, when a forward ([EN/IN1 PH/IN2] = [1 0]) or reverse ([EN/IN1 PH/IN2] = [0 1]) command is followed by a Hi-Z command ([EN/IN1 PH/IN2] = [1 1]). In this condition of Hi-Z (coasting), only the half-bridge involved with the PWM is Hi-Z, while the HS FET on the other half-bridge is kept ON. The determination on which half-bridge to Hi-Z is made based on the previous cycle. This is summarized in Table 7-6.

Table 7-6 PWM EXTEND table (PWM_EXTEND bit = 1'b1)
PREVIOUS STATECURRENT STATEDevice State Transition
OUT1OUT2OUT1OUT2IPROPI
Hi-ZHi-ZHi-ZHi-ZNo currentRemains in STANDBY, no change
HHHi-ZHi-ZNo currentACTIVE to STANDBY
LHHi-ZHISNS2ACTIVE to STANDBY
HLHHi-ZISNS1ACTIVE to STANDBY