SLOS842A September   2013  – June 2015 DRV8301-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Buck Converter Characteristics
    7. 6.7  Current Shunt Amplifier Characteristics
    8. 6.8  Gate Timing and Protection Characteristics
    9. 6.9  SPI Timing Requirements (Slave Mode Only)
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Function Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three-Phase Gate Driver
      2. 7.3.2 Current Shunt Amplifiers
      3. 7.3.3 Buck Converter
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Overcurrent Protection and Reporting (OCP)
        2. 7.3.4.2 Undervoltage Protection (PVDD_UV and GVDD_UV)
        3. 7.3.4.3 Overvoltage Protection (GVDD_OV)
        4. 7.3.4.4 Overtemperature Protection
        5. 7.3.4.5 Fault and Protection Handling
      5. 7.3.5 Start-up and Shutdown Sequence Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 EN_GATE
      2. 7.4.2 DTC
      3. 7.4.3 VDD_SPI
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 SPI
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
      1. 7.6.1 Read / Write Bit
      2. 7.6.2 Address Bits
      3. 7.6.3 SPI Data Bits
        1. 7.6.3.1 Status Registers
        2. 7.6.3.2 Control Registers
        3. 7.6.3.3 Overcurrent Adjustment
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Gate Driver Start-up Issue Errata
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Drive Average Current Load
        2. 8.2.2.2 Overcurrent Protection Setup
        3. 8.2.2.3 Sense Amplifier Setup
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

Use these layout recommendations when designing a PCB for the DRV8301-Q1.

  • The DRV8301-Q1 makes an electrical connection to GND through the PowerPAD. Always check to ensure that the PowerPAD has been properly soldered (See PowerPAD™ Thermally Enhanced Package application report, SLMA002).
  • PVDD bypass capacitors should be placed close to their corresponding pins with a low impedance path to device GND (PowerPAD).
  • GVDD bypass capacitor should be placed close its corresponding pin with a low impedance path to device GND (PowerPAD).
  • AVDD and DVDD bypass capacitors should be placed close to their corresponding pins with a low impedance path to the AGND pin. It is preferable to make this connection on the same layer.
  • AGND should be tied to device GND (PowerPAD) through a low impedance trace/copper fill.
  • Add stitching vias to reduce the impedance of the GND path from the top to bottom side.
  • Try to clear the space around and underneath the DRV8301-Q1 to allow for better heat spreading from the PowerPAD.

10.2 Layout Example

DRV8301-Q1 layout_slos719.pngFigure 13. Top and Bottom Layer Layout Schematic