8.3.2 INHx/INLx: Gate Driver Input Modes

The DRV8305-Q1 can be operated in three different inputs modes to support various commutation schemes.

• Table 2 shows the truth table for the 6-PWM input mode. This mode allows for each half-bridge to be placed in one of three states, either High, Low, or Hi-Z, based on the inputs.

Table 2. 6-PWM Truth Table

INHx	INLx	GHx	GLx
1	1	L	L
1	0	H	L
0	1	L	H
0	0	L	L

Figure 6. 6-PWM Mode
• Table 3 shows the truth table for the 3-PWM input mode. This mode allows for each half-bridge to be placed in one of two states, either High or Low, based on the inputs. The three high-side inputs (INHx) are used to control the state of the half-bridge with the complimentary low-side signals being generated internally. Dead time can be adjusted through the internal setting (DEAD_TIME) in the SPI registers. In this mode all activity on INLx is ignored.

Table 3. 3-PWM Truth Table

INHx	INLx	GHx	GLx
1	X	H	L
0	X	L	H

Figure 7. 3-PWM Mode
• Table 4 and Table 5 show the truth tables for the 1-PWM input mode. The 1-PWM mode uses an internally stored 6-step block commutation table to control the outputs of the three half-bridge drivers based on one PWM and three GPIO inputs. This mode allows the use of a lower cost microcontroller by requiring only one PWM resource. The PWM signal is applied on pin INHA (PWM_IN) to set the duty cycle of the half-bridge outputs along with the three GPIO signals on pins INLA (PHC_0), INHB (PHC_1), INLB (PHC_2) that serve to set the value of a three bit register for the commutation table. The PWM may be operated from 0-100% duty cycle. The three bit register is used to select the state for each half-bridge for a total of eight states including an align and stop state.

An additional and optional GPIO, INHC (DWELL) can be used to facilitate the insertion of dwell states or phase current overlap states between the six commutation steps. This may be used to reduce acoustic noise and improve motion through the reduction of abrupt current direction changes when switching between states. INHC must be high when the state is changed and the dwell state will exist until INHC is taken low. If the dwell states are not being used, the INHC pin can be tied low.

In 1-PWM mode all activity on INLC is ignored.

Figure 8. 1-PWM Mode

The method of freewheeling can be selected through an SPI register (COMM_OPTION). Diode freewheeling is when the phase current is carried by the body diode of the external power MOSFET during periods when the MOSFET is reverse biased (current moving from source to drain). In active freewheeling, the power MOSFET is enabled during periods when the MOSFET is reverse biased. This allows the system to improve efficiency due to the typically lower impedance of the MOSFET conduction channel as compared to the body diode. Table 4 shows the truth table for active freewheeling. Table 5) shows the truth table for diode freewheeling.