SLVSCX2B August   2015  – February 2016 DRV8305

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements (Slave Mode Only)
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Integrated Three-Phase Gate Driver
      2. 7.3.2 INHx/INLx: Gate Driver Input Modes
      3. 7.3.3 VCPH Charge Pump: High-Side Gate Supply
      4. 7.3.4 VCP_LSD LDO: Low-Side Gate Supply
      5. 7.3.5 GHx/GLx: Half-Bridge Gate Drivers
        1. 7.3.5.1 IDRIVE: Gate Driver Output Current
        2. 7.3.5.2 TDRIVE: Gate Driver State Machine
        3. 7.3.5.3 CSAs: Current Shunt Amplifiers
      6. 7.3.6 DVDD and AVDD: Internal Voltage Regulators
      7. 7.3.7 VREG: Voltage Regulator Output
      8. 7.3.8 Protection Features
        1. 7.3.8.1 Fault and Warning Classification
        2. 7.3.8.2 MOSFET Shoot-Through Protection (TDRIVE)
        3. 7.3.8.3 MOSFET Overcurrent Protection (VDS_OCP)
          1. 7.3.8.3.1 MOSFET dV/dt Turn On Protection (TDRIVE)
          2. 7.3.8.3.2 MOSFET Gate Drive Protection (GDF)
        4. 7.3.8.4 Low-Side Source Monitors (SNS_OCP)
        5. 7.3.8.5 Fault and Warning Operating Modes
      9. 7.3.9 Undervoltage Warning (UVFL), Undervoltage Lockout (UVLO), and Overvoltage (OV) Protection
        1. 7.3.9.1 Overtemperature Warning (OTW) and Shutdown (OTSD) Protection
        2. 7.3.9.2 Reverse Supply Protection
        3. 7.3.9.3 MCU Watchdog
        4. 7.3.9.4 VREG Undervoltage (VREG_UV)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up Sequence
      2. 7.4.2 Standby State
      3. 7.4.3 Operating State
      4. 7.4.4 Sleep State
      5. 7.4.5 Limp Home or Fail Code Operation
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 SPI
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
      1. 7.6.1 Status Registers
        1. 7.6.1.1 Warning and Watchdog Reset (Address = 0x1)
        2. 7.6.1.2 OV/VDS Faults (Address = 0x2)
        3. 7.6.1.3 IC Faults (Address = 0x3)
        4. 7.6.1.4 VGS Faults (Address = 0x4)
      2. 7.6.2 Control Registers
        1. 7.6.2.1 HS Gate Drive Control (Address = 0x5)
        2. 7.6.2.2 LS Gate Drive Control (Address = 0x6)
        3. 7.6.2.3 Gate Drive Control (Address = 0x7)
        4. 7.6.2.4 IC Operation (Address = 0x9)
        5. 7.6.2.5 Shunt Amplifier Control (Address = 0xA)
        6. 7.6.2.6 Voltage Regulator Control (Address = 0xB)
        7. 7.6.2.7 VDS Sense Control (Address = 0xC)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Drive Average Current
        2. 8.2.2.2 MOSFET Slew Rates
        3. 8.2.2.3 Overcurrent Protection
        4. 8.2.2.4 Current Sense Amplifiers
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • 4.4-V to 45-V Operating Voltage
  • 1.25-A and 1-A Peak Gate Drive Currents
  • Programmable High- and Low-Side Slew-Rate Control
  • Charge-Pump Gate Driver for 100% Duty Cycle
  • Three Integrated Current-Shunt Amplifiers
  • Integrated 50-mA LDO (3.3-V and 5-V Option)
  • 3-PWM or 6-PWM Input Control up to 200 kHz
  • Single PWM-Mode Commutation Capability
  • Supports Both 3.3-V and 5-V Digital Interface
  • Serial Peripheral Interface (SPI) for Device Settings and Fault Reporting
  • Thermally-Enhanced 48-Pin HTQFP
  • Protection Features:
    • Fault Diagnostics and MCU Watchdog
    • Programmable Dead-Time Control
    • MOSFET Shoot-Through Prevention
    • MOSFET VDS Overcurrent Monitors
    • Gate-Driver Fault Detection
    • Reverse Battery-Protection Support
    • Limp Home-Mode Support
    • Overtemperature Warning and Shutdown

2 Applications

  • Three-Phase BLDC and PMSM Motors
  • CPAP and Pumps
  • Robotics and RC Toys
  • Power Tools
  • Industrial Automation

3 Description

The DRV8305 device is a gate driver IC for three-phase motor-drive applications. The device provides three high-accuracy and temperature compensated half-bridge drivers, each capable of driving a high-side and low-side N-channel MOSFET. A charge pump driver supports 100% duty cycle and low-voltage operation. The device can tolerate load dump voltages up to 45-V.

The DRV8305 device includes three bidirectional current-shunt amplifiers for accurate low-side current measurements that support variable gain settings and an adjustable offset reference.

The DRV8305 device has an integrated voltage regulator (3.3-V or 5-V) to support an MCU or other system power requirements. The voltage regulator can be interfaced directly with a standard LIN physical interface to allow low system standby and sleep currents.

The gate driver uses automatic handshaking when switching to prevent current shoot through. The VDS of both the high-side and low-side MOSFETs is accurately sensed to protect the external MOSFETs from overcurrent conditions. The SPI provides detailed fault reporting, diagnostics, and device configurations such as gain options for the current shunt amplifier, individual MOSFET overcurrent detection, and gate-drive slew-rate control.

Device Options:

  • DRV8305N: Voltage reference
  • DRV83053: 3.3-V, 50-mA LDO
  • DRV83055: 5-V, 50-mA LDO

Device Information (1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DRV8305 HTQFP (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

DRV8305 fbd_FAD_lvscx2.gif