JAJSF51A April   2018  – July 2018 DRV8306

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three Phase Smart Gate Drivers
        1. 8.3.1.1 PWM Control Mode (1x PWM Mode)
        2. 8.3.1.2 Hardware Interface Mode
        3. 8.3.1.3 Gate Driver Voltage Supplies
        4. 8.3.1.4 Smart Gate Drive Architecture
          1. 8.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
          2. 8.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
          3. 8.3.1.4.3 Gate Drive Clamp
          4. 8.3.1.4.4 Propagation Delay
          5. 8.3.1.4.5 MOSFET VDS Monitors
          6. 8.3.1.4.6 VDRAIN Sense Pin
      2. 8.3.2 DVDD Linear Voltage Regulator
      3. 8.3.3 Pulse-by-Pulse Current Limit
      4. 8.3.4 Hall Comparators
      5. 8.3.5 FGOUT Signal
      6. 8.3.6 Pin Diagrams
      7. 8.3.7 Gate-Driver Protective Circuits
        1. 8.3.7.1 VM Supply Undervoltage Lockout (UVLO)
        2. 8.3.7.2 VCP Charge-Pump Undervoltage Lockout (CPUV)
        3. 8.3.7.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
        4. 8.3.7.4 VSENSE Overcurrent Protection (SEN_OCP)
        5. 8.3.7.5 Gate Driver Fault (GDF)
        6. 8.3.7.6 Thermal Shutdown (OTSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Gate Driver Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (ENABLE Reset Pulse)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Hall Sensor Configuration and Connection
        1. 9.1.1.1 Typical Configuration
        2. 9.1.1.2 Open Drain Configuration
        3. 9.1.1.3 Series Configuration
        4. 9.1.1.4 Parallel Configuration
    2. 9.2 Typical Application
      1. 9.2.1 Primary Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 External MOSFET Support
            1. 9.2.1.2.1.1 Example
          2. 9.2.1.2.2 IDRIVE Configuration
            1. 9.2.1.2.2.1 Example
          3. 9.2.1.2.3 VDS Overcurrent Monitor Configuration
            1. 9.2.1.2.3.1 Example
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM, DVDD)
IVM VM operating supply current VVM = 24 V; ENABLE = 1; PWM = 0 V 5 8 mA
IVMQ VM sleep mode supply current ENABLE = 0; VVM = 24 V, TA = 25°C 20 40 µA
ENABLE = 0, VVM = 24 V, TA = 125°C  100
tRST Reset pulse time ENABLE = 0 V period to reset faults 15 40 µs
tSLEEP Sleep time ENABLE = 0 V to driver tri-stated 200 µs
tWAKE Wake-up time VVM > VUVLO; ENABLE = 3.3 V to output transistion 1 ms
VDVDD Internal logic regulator voltage IDVDD = 0 to 30 mA 2.9 3.3 3.6 V
CHARGE PUMP (VCP, CPH, CPL)
VVCP VCP operating voltage with respect to VM VM = 12 to 38 V; IVCP = 0 to 15 mA 7 10 11.5 V
VM = 10 V; IVCP = 0 to 10 mA 6.5 7.5 9.5
VM = 8 V; IVCP = 0 to 5 mA 5 6 7.5
VM = 6 V; IVCP = 0 to 1 mA 3.8 4.3 6.5
LOGIC-LEVEL INPUTS (PWM, DIR, nBRAKE)
VIL Input logic low voltage 0 0.8 V
VIH Input logic high voltage 1.5 5.5 V
VHYS Input logic hysteresis 100 mV
IIL Input logic low current VPIN (Pin Voltage) = 0 V –1 1 µA
IIH Input logic high current VPIN (Pin Voltage) = 5 V 100 µA
RPD Pulldown resistance (PWM, DIR, nBRAKE) Internal pulldown to AGND 100 kΩ
LOGIC-LEVEL INPUTS (ENABLE)
VIL Input logic low voltage 0 0.6 V
VIH Input logic high voltage 1.5 5.5 V
VHYS Input logic hysteresis 100 mV
IIL Input logic low current VPIN (Pin Voltage) = 0 V –10 10 µA
IIH Input logic high current VPIN (Pin Voltage) = 5 V –5 5 µA
SEVEN-LEVEL INPUTS (IDRIVE, VDS)
VI1 Input mode 1 voltage Tied to AGND 0 V
VI2 Input mode 2 voltage 18 kΩ ± 5% to AGND 0.5 V
VI3 Input mode 3 voltage 75 kΩ ± 5% to AGND 1.1 V
VI4 Input mode 4 voltage Hi-Z 1.65 V
VI5 Input mode 5 voltage 75 kΩ ± 5% to DVDD 2.2 V
VI6 Input mode 6 voltage 18 kΩ ± 5% to DVDD 2.8 V
VI7 Input mode 7 voltage Tied to DVDD 3.3 V
OPEN-DRAIN OUTPUTS (nFAULT, FGOUT)
VOL Output logic low voltage IOD = 2 mA 0.1 V
IOZ Output logic high current VOD = 5 V –1 1 µA
GATE DRIVERS (GHX, SHX, GLX)
VGHS High-side VGS gate drive (gate-to-source) VVM = 12 to 38 V; IHS_GATE = 0 to 15 mA 7 10 11.5 V
VVM = 10 V; IHS_GATE = 0 to 10 mA 6.5 7.5 8.5
VVM = 8 V; IHS_GATE = 0 to 5 mA 5 6 7
VVM = 6 V; IHS_GATE = 0 to 1 mA 3.8 4.3 6.5
VGSL Low-side VGS gate drive (gate-to-source) VVM = 12 to 38 V; ILS_GATE = 0 to 15 mA 7.5 10 12.5 V
VVM = 10 V; ILS_GATE = 0 to 10 mA 5.5 7.5 9.5
VVM = 8 V; ILS_GATE = 0 to 5 mA 3.5 6 8.5
VVM = 6 V; ILS_GATE = 0 to 1 mA 3 4.3 6.5
tDEAD Output dead time 120 ns
tDRIVE Peak gate drive time 4000 ns
IDRIVEP Peak source gate current (high-side and low-side) IDRIVE tied to AGND 15 mA
IDRIVE 18 kΩ (±5%) to AGND 45
IDRIVE 75 kΩ (±5%) to AGND 60
IDRIVE Hi-Z ( > 500 kΩ to AGND) 90
IDRIVE 75 kΩ (±5%) to DVDD 105
IDRIVE 18 kΩ (±5%) to DVDD 135
IDRIVE tied to DVDD 150
IDRIVEN Peak sink gate current (high-side and low-side) IDRIVE tied to AGND 30 mA
IDRIVE 18 kΩ (±5%) to AGND 90
IDRIVE 75 kΩ (±5%) to AGND 120
IDRIVE Hi-Z ( > 500 kΩ to AGND) 180
IDRIVE 75 kΩ (±5%) to DVDD 210
IDRIVE 18 kΩ (±5%) to DVDD 270
IDRIVE tied to DVDD 300
IHOLD FET holding current Source current after tDRIVE 15 mA
Sink current after tDRIVE 30
ISTRONG FET hold-off strong pulldown GHX and GLX 300 mA
ROFF FET gate hold-off resistor GHX to SHX and GLX to PGND 150 kΩ
tPD Propagation delay PWM transition to GHX/GLX transition 180 250 ns
HALL SENSOR INPUTS (HPX, HNX)
VHYS Hall comparator hysteresis voltage 20 30 40 mV
ΔVHYS Hall comparator hysteresis difference Between A, B and C -5 5 mV
VID Hall comparator input differential 50 mV
VCM Hall comparator input common mode voltage CM range 1.5 3.5 V
II Input leakage current HPX = HNX = 0 V –1 1 µA
tHDEG Hall deglitch time 5 µs
CYCLE-BY-CYCLE CURRENT LIMIT (ISEN)
VLIMIT Voltage limit across RSENSE for the current limiter 0.225 0.25 0.275 V
tBLANK Time that VLIMIT is ignored from the start of the PWM cycle 5 µs
PROTECTION CIRCUITS
VUVLO VM undervoltage lockout VM falling, UVLO report 5.4 5.8 V
VM rising, UVLO recovery 5.6 6
VUVLO_HYS VM undervoltage hysteresis Rising to falling threshold 200 mV
tUVLO_DEG VM undervoltage deglitch time VM falling, UVLO report 10 µs
VCPUV Charge pump undervoltage With respect to VM 2.4 V
VGS_CLAMP Gate drive clamping voltage Positive clamping voltage 10.5 15 V
Negative clamping voltage –0.6
VDS_OCP VDS overcurrent trip voltage VDS tied to AGND 0.15 V
VDS 18 kΩ (±5%) to AGND 0.24
VDS 75 kΩ (±5%) to AGND 0.4
VDS Hi-Z ( > 500 kΩ to AGND) 0.6
VDS 75 kΩ (±5%) to DVDD 0.9
VDS 18 kΩ (±5%) to DVDD 1.8
VDS tied to DVDD Disabled
VSEN_OCP VSENSE overcurrent trip voltage 1.7 1.8 1.9 V
tOCP_DEG VDS and VSENSE overcurrent deglitch time 4.5 µs
tRETRY Overcurrent retry time 4 ms
TOTSD Thermal shutdown temperature Die temperature Tj 150 170 °C
THYS Thermal hysteresis Die temperature Tj 20 °C