JAJSF51A April 2018 – July 2018 DRV8306
PRODUCTION DATA.
The ENABLE pin manages the state of the DRV8306 device. When the ENABLE pin is low, the device goes to a low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are disabled, the charge pump is disabled, and the DVDD regulator is disabled. The tSLEEP time must elapse after a falling edge on the ENABLE pin before the device goes to the sleep mode. The device goes from the sleep mode automatically if the ENABLE pin is pulled high. The tWAKE time must elapse before the device is ready for inputs.
In sleep mode and when VVM < VUVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an internal resistor.
NOTE
During power up and power down of the device through the ENABLE pin, the nFAULT pin is held low as the internal regulators are enabled or disabled. After the regulators have enabled or disabled, the nFAULT pin is automatically released. The duration that the nFAULT pin is low does not exceed the tSLEEP or tWAKE time.