JAJSMZ5B September 2021 – February 2022 DRV8311
PRODUCTION DATA
#DRV8311_DRV8311_TABLE_1 lists the memory-mapped registers for the DRV8311 registers. All register offset addresses not listed in #DRV8311_DRV8311_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | DEV_STS1 | Device Status 1 Register | #DRV8311_DRV8311_DRV8311_DEV_STS1 |
4h | OT_STS | Over Temperature Status Register | #DRV8311_DRV8311_DRV8311_OT_STS |
5h | SUP_STS | Supply Status Register | #DRV8311_DRV8311_DRV8311_SUP_STS |
6h | DRV_STS | Driver Status Register | #DRV8311_DRV8311_DRV8311_DRV_STS |
7h | SYS_STS | System Status Register | #DRV8311_DRV8311_DRV8311_SYS_STS |
Ch | PWM_SYNC_PRD | PWM Sync Period Register | #DRV8311_DRV8311_DRV8311_PWM_SYNC_PRD |
10h | FLT_MODE | Fault Mode Register | #DRV8311_DRV8311_DRV8311_FLT_MODE |
12h | SYSF_CTRL | System Fault Control Register | #DRV8311_DRV8311_DRV8311_SYSF_CTRL |
13h | DRVF_CTRL | Driver Fault Control Register | #DRV8311_DRV8311_DRV8311_DRVF_CTRL |
16h | FLT_TCTRL | Fault Timing Control Register | #DRV8311_DRV8311_DRV8311_FLT_TCTRL |
17h | FLT_CLR | Fault Clear Register | #DRV8311_DRV8311_DRV8311_FLT_CLR |
18h | PWMG_PERIOD | PWM_GEN Period Register | #DRV8311_DRV8311_DRV8311_PWMG_PERIOD |
19h | PWMG_A_DUTY | PWM_GEN A Duty Register | #DRV8311_DRV8311_DRV8311_PWMG_A_DUTY |
1Ah | PWMG_B_DUTY | PWM_GEN B Duty Register | #DRV8311_DRV8311_DRV8311_PWMG_B_DUTY |
1Bh | PWMG_C_DUTY | PWM_GEN C Duty Register | #DRV8311_DRV8311_DRV8311_PWMG_C_DUTY |
1Ch | PWM_STATE | PWM State Register | #DRV8311_DRV8311_DRV8311_PWM_STATE |
1Dh | PWMG_CTRL | PWM_GEN Control Register | #DRV8311_DRV8311_DRV8311_PWMG_CTRL |
20h | PWM_CTRL1 | PWM Control Register 1 | #DRV8311_DRV8311_DRV8311_PWM_CTRL1 |
22h | DRV_CTRL | Predriver control Register | #DRV8311_DRV8311_DRV8311_DRV_CTRL |
23h | CSA_CTRL | CSA Control Register | #DRV8311_DRV8311_DRV8311_CSA_CTRL |
3Fh | SYS_CTRL | System Control Register | #DRV8311_DRV8311_DRV8311_SYS_CTRL |
Complex bit access types are encoded to fit into small table cells. #DRV8311_DRV8311_LEGEND shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
DEV_STS1 is shown in #DRV8311_DRV8311_DRV8311_DEV_STS1_FIGURE and described in #DRV8311_DRV8311_DRV8311_DEV_STS1_TABLE.
Return to the Summary Table.
Device Status 1 Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | OTP_FLT | |||||
R-0h | R-0-0h | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET | SPI_FLT | OCP | RESERVED | UVP | OT | FAULT | |
R-1h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-9 | RESERVED | R-0 | 0h | Reserved |
8 | OTP_FLT | R | 0h | OTP read fault
0h = No OTP read fault is detected 1h = OTP read fault detected |
7 | RESET | R | 1h | Supply Power On Reset Status
0h = No power on reset condition is detected 1h = Power-on-reset condition is detected |
6 | SPI_FLT | R | 0h | SPI Fault Status
0h = No SPI communication fault is detected 1h = SPI communication fault is detected |
5 | OCP | R | 0h | Driver Overcurrent Protection Status
0h = No overcurrent condition is detected 1h = Overcurrent condition is detected |
4-3 | RESERVED | R | 0h | Reserved |
2 | UVP | R | 0h | Supply Undervoltage Status
0h = No undervoltage voltage condition is detected on CP, AVDD or VIN_AVDD 1h = Undervoltage voltage condition is detected on CP, AVDD or VIN_AVDD |
1 | OT | R | 0h | Overtemperature Fault Status
0h = No overtemperature warning / shutdown is detected 1h = Overtemperature warning / shutdown is detected |
0 | FAULT | R | 0h | Device Fault Status
0h = No fault condition is detected 1h = Fault condition is detected |
OT_STS is shown in #DRV8311_DRV8311_DRV8311_OT_STS_FIGURE and described in #DRV8311_DRV8311_DRV8311_OT_STS_TABLE.
Return to the Summary Table.
Over Temperature Status Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | ||||||
R-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OTS_AVDD | OTW | OTSD | ||||
R-0-0h | R-0h | R-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-3 | RESERVED | R-0 | 0h | Reserved |
2 | OTS_AVDD | R | 0h | AVDD LDO Overtemperature Fault Status
0h = No overtemperature shutdown near AVDD is detected 1h = Overtemperature shutdown near AVDD is detected |
1 | OTW | R | 0h | Overtemperature Warning Status
0h = No overtemperature warning is detected 1h = Overtemperature warning is detected |
0 | OTSD | R | 0h | Overtemperature Shutdown Fault Status
0h = No overtemperature shutdown is detected 1h = Overtemperature shutdown is detected |
SUP_STS is shown in #DRV8311_DRV8311_DRV8311_SUP_STS_FIGURE and described in #DRV8311_DRV8311_DRV8311_SUP_STS_TABLE.
Return to the Summary Table.
Supply Status Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | ||||||
R-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CSAREF_UV | CP_UV | RESERVED | AVDD_UV | RESERVED | VINAVDD_UV | |
R-0-0h | R-0h | R-0h | R-0-0h | R-0h | R-0-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-6 | RESERVED | R-0 | 0h | Reserved |
5 | CSAREF_UV | R | 0h | CSA REF Undervoltage Fault Status
0h = No CSAREF undervoltage is detected 1h = CSAREF undervoltage is detected |
4 | CP_UV | R | 0h | Charge Pump Undervoltage Fault Status
0h = No charge pump undervoltage is detected 1h = Charge pump undervoltage is detected |
3 | RESERVED | R-0 | 0h | Reserved |
2 | AVDD_UV | R | 0h | AVDD LDO Undervoltage Fault Status
0h = No AVDD output undervoltage is detected 1h = AVDD output undervoltage is detected |
1 | RESERVED | R-0 | 0h | Reserved |
0 | VINAVDD_UV | R | 0h | VIN_AVDD Undervoltage Fault Status
0h = No AVDD supply input undervoltage is detected 1h = AVDD supply input undervoltage is detected |
DRV_STS is shown in #DRV8311_DRV8311_DRV8311_DRV_STS_FIGURE and described in #DRV8311_DRV8311_DRV8311_DRV_STS_TABLE.
Return to the Summary Table.
Driver Status Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | ||||||
R-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OCPC_HS | OCPB_HS | OCPA_HS | RESERVED | OCPC_LS | OCPB_LS | OCPA_LS |
R-0-0h | R-0h | R-0h | R-0h | R-0-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-7 | RESERVED | R-0 | 0h | Reserved |
6 | OCPC_HS | R | 0h | Overcurrent Status on High-side MOSFET of OUTC
0h = No overcurrent detected on high-side MOSFET of OUTC 1h = Overcurrent detected on high-side MOSFET of OUTC |
5 | OCPB_HS | R | 0h | Overcurrent Status on High-side MOSFET of OUTB
0h = No overcurrent detected on high-side MOSFET of OUTB 1h = Overcurrent detected on high-side MOSFET of OUTB |
4 | OCPA_HS | R | 0h | Overcurrent Status on High-side MOSFET of OUTA
0h = No overcurrent detected on high-side MOSFET of OUTA 1h = Overcurrent detected on high-side MOSFET of OUTA |
3 | RESERVED | R-0 | 0h | Reserved |
2 | OCPC_LS | R | 0h | Overcurrent Status on Low-side MOSFET of OUTC
0h = No overcurrent detected on low-side MOSFET of OUTC 1h = Overcurrent detected on low-side MOSFET of OUTC |
1 | OCPB_LS | R | 0h | Overcurrent Status on Low-side MOSFET of OUTB
0h = No overcurrent detected on low-side MOSFET of OUTB 1h = Overcurrent detected on low-side MOSFET of OUTB |
0 | OCPA_LS | R | 0h | Overcurrent Status on Low-side MOSFET of OUTA
0h = No overcurrent detected on low-side MOSFET of OUTA 1h = Overcurrent detected on low-side MOSFET of OUTA |
SYS_STS is shown in #DRV8311_DRV8311_DRV8311_SYS_STS_FIGURE and described in #DRV8311_DRV8311_DRV8311_SYS_STS_TABLE.
Return to the Summary Table.
System Status Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | ||||||
R-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OTPLD_ERR | RESERVED | SPI_PARITY | BUS_CNT | FRM_ERR | ||
R-0-0h | R-0h | R-0-0h | R-0h | R-0h | R-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-5 | RESERVED | R-0 | 0h | Reserved |
4 | OTPLD_ERR | R | 0h | OTP Read Error
0h = No OTP read error is detected 1h = OTP read error is detected |
3 | RESERVED | R-0 | 0h | Reserved |
2 | SPI_PARITY | R | 0h | SPI Parity Error
0h = No SPI Parity Error is detected 1h = SPI Parity Error is detected |
1 | BUS_CNT | R | 0h | SPI Bus Contention Error
0h = No SPI Bus Contention Error is detected 1h = SPI Bus Contention Error is detected |
0 | FRM_ERR | R | 0h | SPI Frame Error
0h = No SPI Frame Error is detected 1h = SPI Frame Error is detected |
PWM_SYNC_PRD is shown in #DRV8311_DRV8311_DRV8311_PWM_SYNC_PRD_FIGURE and described in #DRV8311_DRV8311_DRV8311_PWM_SYNC_PRD_TABLE.
Return to the Summary Table.
PWM Sync Period Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | PWM_SYNC_PRD | |||||
R-0h | R-0-0h | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWM_SYNC_PRD | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-12 | RESERVED | R-0 | 0h | Reserved |
11-0 | PWM_SYNC_PRD | R | 0h | 12-bit output indicating period of PWM_SYNC signal |
FLT_MODE is shown in #DRV8311_DRV8311_DRV8311_FLT_MODE_FIGURE and described in #DRV8311_DRV8311_DRV8311_FLT_MODE_TABLE.
Return to the Summary Table.
Fault Mode Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | OTPFLT_MODE | |||||
R-0h | R-0-0h | R/W-1h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPIFLT_MODE | OCP_MODE | UVP_MODE | OTSD_MODE | ||||
R/W-0h | R/W-1h | R/W-1h | R/W-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-9 | RESERVED | R-0 | 0h | Reserved |
8 | OTPFLT_MODE | R/W | 1h | System Fault Mode.
0h = OTP read fault is enabled 1h = OTP read fault is disabled |
7 | SPIFLT_MODE | R/W | 0h | SPI Fault mode
0h = SPI Fault is enabled 1h = SPI Fault is disabled |
6-4 | OCP_MODE | R/W | 1h | Overcurrent Protection Fault mode
0h = Report on nFault, predriver HiZ, auto recovery with Slow Retry time (in ms) 1h = Report on nFault, predriver HiZ, auto recovery with Fast Retry time (in ms) 2h = Report on nFault, predriver HiZ, Latched Fault 3h = Report on nFault, No action on predriver 4h = Reserved 5h = Reserved 6h = Reserved 7h = Disabled |
3-2 | UVP_MODE | R/W | 1h | Undervoltage Protection Fault mode
0h = Report on nFault, predriver HiZ, auto recovery with Slow Retry time (in ms) 1h = Report on nFault, predriver HiZ, auto recovery with Fast Retry time (in ms) 2h = Reserved 3h = Reserved |
1-0 | OTSD_MODE | R/W | 1h | Overtemperature Fault mode
0h = Report on nFault, predriver HiZ, auto recovery with Slow Retry time (in ms) 1h = Report on nFault, predriver HiZ, auto recovery with Fast Retry time (in ms) 2h = Reserved 3h = Reserved |
SYSF_CTRL is shown in #DRV8311_DRV8311_DRV8311_SYSF_CTRL_FIGURE and described in #DRV8311_DRV8311_DRV8311_SYSF_CTRL_TABLE.
Return to the Summary Table.
System Fault Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | OTAVDD_EN | OTW_EN | RESERVED | |||
R-0h | R-0-0h | R/W-1h | R/W-0h | R-0-4h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CSAREFUV_EN | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |
R-0-4h | R/W-0h | R/W-1h | R-0-0h | R/W-1h | R-0-0h | R/W-1h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-11 | RESERVED | R-0 | 0h | Reserved |
10 | OTAVDD_EN | R/W | 1h | AVDD Overtemperature Fault Enable
0h = Overtemperature protection near AVDD is disabled 1h = Overtemperature protection near AVDD is enabled |
9 | OTW_EN | R/W | 0h | Overtemperature Warning Fault Enable
0h = Over temperature warning reporting on nFAULT is disabled 1h = Over temperature warning reporting on nFAULT is enabled |
8-6 | RESERVED | R-0 | 4h | Reserved |
5 | CSAREFUV_EN | R/W | 0h | CSAREF Undervoltage Fault Enable
0h = CSAREF undervoltage lockout is disabled 1h = CSAREF undervoltage lockout is enabled |
4 | RESERVED | R/W | 1h | Reserved |
3 | RESERVED | R-0 | 0h | Reserved |
2 | RESERVED | R/W | 1h | Reserved |
1 | RESERVED | R-0 | 0h | Reserved |
0 | RESERVED | R/W | 1h | Reserved |
DRVF_CTRL is shown in #DRV8311_DRV8311_DRV8311_DRVF_CTRL_FIGURE and described in #DRV8311_DRV8311_DRV8311_DRVF_CTRL_TABLE.
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Driver Fault Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | ||||||
R-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OCP_DEG | OCP_TBLANK | RESERVED | OCP_LVL | |||
R-0-0h | R/W-3h | R/W-0h | R-0-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-6 | RESERVED | R-0 | 0h | Reserved |
5-4 | OCP_DEG | R/W | 3h | OCP Deglitch time
0h = OCP deglitch time is 0.2 µs 1h = OCP deglitch time is 0.5 µs 2h = OCP deglitch time is 0.8 µs 3h = OCP deglitch time is 1 µs |
3-2 | OCP_TBLANK | R/W | 0h | OCP Blanking time
0h = OCP blanking time is 0.2 µs 1h = OCP blanking time is 0.5 µs 2h = OCP blanking time is 0.8 µs 3h = OCP blanking time is 1 µs |
1 | RESERVED | R-0 | 0h | Reserved |
0 | OCP_LVL | R/W | 0h | OCP Level Settings
0h = OCP level is 9 A (TYP) 1h = OCP level is 5 A (TYP) |
FLT_TCTRL is shown in #DRV8311_DRV8311_DRV8311_FLT_TCTRL_FIGURE and described in #DRV8311_DRV8311_DRV8311_FLT_TCTRL_TABLE.
Return to the Summary Table.
Fault Timing Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | ||||||
R-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLOW_TRETRY | FAST_TRETRY | |||||
R-0-0h | R/W-0h | R/W-3h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-4 | RESERVED | R-0 | 0h | Reserved |
3-2 | SLOW_TRETRY | R/W | 0h | Slow Recovery Retry Time from Fault Condition
0h = 0.5s 1h = 1s 2h = 2s 3h = 5s |
1-0 | FAST_TRETRY | R/W | 3h | Fast Recovery Retry Time from Fault Condition
0h = 0.5ms 1h = 1ms 2h = 2ms 3h = 5ms |
FLT_CLR is shown in #DRV8311_DRV8311_DRV8311_FLT_CLR_FIGURE and described in #DRV8311_DRV8311_DRV8311_FLT_CLR_TABLE.
Return to the Summary Table.
Fault Clear Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | ||||||
R-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FLT_CLR | ||||||
R-0-0h | W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-1 | RESERVED | R-0 | 0h | Reserved |
0 | FLT_CLR | W | 0h | Clear Fault
0h = No clear fault command is issued 1h = To clear the latched fault bits. This bit automatically resets after being written. |
PWMG_PERIOD is shown in #DRV8311_DRV8311_DRV8311_PWMG_PERIOD_FIGURE and described in #DRV8311_DRV8311_DRV8311_PWMG_PERIOD_TABLE.
Return to the Summary Table.
PWM_GEN Period Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | PWM_PRD_OUT | |||||
R-0h | R-0-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWM_PRD_OUT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-12 | RESERVED | R-0 | 0h | Reserved |
11-0 | PWM_PRD_OUT | R/W | 0h | 12-bit Period for output PWM signals in PWM Generation Mode |
PWMG_A_DUTY is shown in #DRV8311_DRV8311_DRV8311_PWMG_A_DUTY_FIGURE and described in #DRV8311_DRV8311_DRV8311_PWMG_A_DUTY_TABLE.
Return to the Summary Table.
PWM_GEN A Duty Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | PWM_DUTY_OUTA | |||||
R-0h | R-0-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWM_DUTY_OUTA | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-12 | RESERVED | R-0 | 0h | Reserved |
11-0 | PWM_DUTY_OUTA | R/W | 0h | 12-bit Duty Cycle for Phase A output in PWM Generation Mode |
PWMG_B_DUTY is shown in #DRV8311_DRV8311_DRV8311_PWMG_B_DUTY_FIGURE and described in #DRV8311_DRV8311_DRV8311_PWMG_B_DUTY_TABLE.
Return to the Summary Table.
PWM_GEN B Duty Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | PWM_DUTY_OUTB | |||||
R-0h | R-0-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWM_DUTY_OUTB | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-12 | RESERVED | R-0 | 0h | Reserved |
11-0 | PWM_DUTY_OUTB | R/W | 0h | 12-bit Duty Cycle for Phase B output in PWM Generation Mode |
PWMG_C_DUTY is shown in #DRV8311_DRV8311_DRV8311_PWMG_C_DUTY_FIGURE and described in #DRV8311_DRV8311_DRV8311_PWMG_C_DUTY_TABLE.
Return to the Summary Table.
PWM_GEN C Duty Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | PWM_DUTY_OUTC | |||||
R-0h | R-0-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWM_DUTY_OUTC | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-12 | RESERVED | R-0 | 0h | Reserved |
11-0 | PWM_DUTY_OUTC | R/W | 0h | 12-bit Duty Cycle for Phase C output in PWM Generation Mode |
PWM_STATE is shown in #DRV8311_DRV8311_DRV8311_PWM_STATE_FIGURE and described in #DRV8311_DRV8311_DRV8311_PWM_STATE_TABLE.
Return to the Summary Table.
PWM State Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | PWMC_STATE | |||||
R-0h | R-0-0h | R/W-7h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PWMB_STATE | RESERVED | PWMA_STATE | ||||
R-0-0h | R/W-7h | R-0-0h | R/W-7h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-11 | RESERVED | R-0 | 0h | Reserved |
10-8 | PWMC_STATE | R/W | 7h | Phase C Driver Output control
0h = High Side is OFF, Low Side is OFF 1h = High Side is OFF, Low Side is forced ON 2h = High Side is forced ON, Low Side is OFF 3h = Reserved 4h = Reserved 5h = High Side is OFF, Low Side PWM 6h = High Side PWM, Low Side is OFF 7h = High Side PWM, Low Side !PWM |
7 | RESERVED | R-0 | 0h | Reserved |
6-4 | PWMB_STATE | R/W | 7h | Phase B Driver Output control
0h = High Side is OFF, Low Side is OFF 1h = High Side is OFF, Low Side is forced ON 2h = High Side is forced ON, Low Side is OFF 3h = Reserved 4h = Reserved 5h = High Side is OFF, Low Side PWM 6h = High Side PWM, Low Side is OFF 7h = High Side PWM, Low Side !PWM |
3 | RESERVED | R-0 | 0h | Reserved |
2-0 | PWMA_STATE | R/W | 7h | Phase A Driver Output control
0h = High Side is OFF, Low Side is OFF 1h = High Side is OFF, Low Side is forced ON 2h = High Side is forced ON, Low Side is OFF 3h = Reserved 4h = Reserved 5h = High Side is OFF, Low Side PWM 6h = High Side PWM, Low Side is OFF 7h = High Side PWM, Low Side !PWM |
PWMG_CTRL is shown in #DRV8311_DRV8311_DRV8311_PWMG_CTRL_FIGURE and described in #DRV8311_DRV8311_DRV8311_PWMG_CTRL_TABLE.
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PWM_GEN Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | PWM_EN | PWMCNTR_MODE | ||||
R-0h | R-0-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWM_OSC_SYNC | SPICLK_FREQ_SYNC | SPISYNC_ACRCY | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-11 | RESERVED | R-0 | 0h | Reserved |
10 | PWM_EN | R/W | 0h | Enable 3X Internal mode PWM Generation
0h = PWM_GEN disabled 1h = PWM_GEN enabled |
9-8 | PWMCNTR_MODE | R/W | 0h | PWM Gen counter mode
0h = Up and Down 1h = Up 2h = Down 3h = No action |
7-5 | PWM_OSC_SYNC | R/W | 0h | Oscillator synchronization and PWM_SYNC control
0h = Oscillator synchronization is disable 1h = PWM_SYNC_PRD indicates period of PWM_SYNC signal and can be used to calibrate PWM period 2h = PWM_SYNC used to set PWM period 3h = Oscillator synchronization is disable 4h = Oscillator synchronization is disable 5h = PWM_SYNC used for oscillator synchronization (only 20 kHz frequency supported) 6h = PWM_SYNC used for oscillator synchronization and setting PWM period (only 20 kHz frequency supported) 7h = SPI Clock pin SCLK used for oscillator synchronization (Configure SPICLK_FREQ_SYNC) |
4-2 | SPICLK_FREQ_SYNC | R/W | 0h | SPI Clock Frequency for synchronizing the Oscillator
0h = 1 MHz 1h = 1.25 MHz 2h = 2 MHz 3h = 2.5 MHz 4h = 4 MHz 5h = 5 MHz 6h = 8 MHz 7h = 10 MHz |
1-0 | SPISYNC_ACRCY | R/W | 0h | Number of SPI Clock Cycle require for synchronizing the Oscillator
0h = 512 Clock Cycles (1%) 1h = 256 Clock Cycles (1%) 2h = 128 Clock Cycles (1%) 3h = 64 Clock Cycles (2%) |
PWM_CTRL1 is shown in #DRV8311_DRV8311_DRV8311_PWM_CTRL1_FIGURE and described in #DRV8311_DRV8311_DRV8311_PWM_CTRL1_TABLE.
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PWM Control Register 1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | ||||||
R-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SSC_DIS | PWM_MODE | |||||
R-0-0h | R/W-1h | R/W-3h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-3 | RESERVED | R-0 | 0h | Reserved |
2 | SSC_DIS | R/W | 1h | Disable Spread Spectrum Modulation for internal Oscillator
0h = Spread spectrum modulation is enabled 1h = Spread spectrum modulation is disabled |
1-0 | PWM_MODE | R/W | 3h | PWM mode selection
(The reset setting in DRV8311S is 00b and in DRV8311P is 11b)
0h = 6x mode 1h = 6x mode 2h = 3x mode 3h = PWM Generation mode |
DRV_CTRL is shown in #DRV8311_DRV8311_DRV8311_DRV_CTRL_FIGURE and described in #DRV8311_DRV8311_DRV8311_DRV_CTRL_TABLE.
Return to the Summary Table.
Predriver control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | RESERVED | |||||
R-0h | R-0-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DLYCMP_EN | TDEAD_CTRL | RESERVED | SLEW_RATE | ||||
R/W-0h | R/W-0h | R-0-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-12 | RESERVED | R-0 | 0h | Reserved |
11-8 | RESERVED | R/W | 0h | Reserved |
7 | DLYCMP_EN | R/W | 0h | Driver Delay Compensation enable
0h = Driver Delay Compensation is disabled 1h = Driver Delay Compensation is enabled |
6-4 | TDEAD_CTRL | R/W | 0h | Deadtime insertion control
0h = No deadtime (Handshake Only) 1h = 200ns 2h = 400ns 3h = 600ns 4h = 800ns 5h = 1us 6h = 1.2us 7h = 1.4us |
3-2 | RESERVED | R-0 | 0h | Reserved |
1-0 | SLEW_RATE | R/W | 0h | Slew rate settings
0h = Slew rate is 35 V/µs 1h = Slew rate is 75 V/µs 2h = Slew rate is 180 V/µs 3h = Slew rate is 230 V/µs |
CSA_CTRL is shown in #DRV8311_DRV8311_DRV8311_CSA_CTRL_FIGURE and described in #DRV8311_DRV8311_DRV8311_CSA_CTRL_TABLE.
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CSA Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | RESERVED | ||||||
R-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CSA_EN | RESERVED | CSA_GAIN | ||||
R-0-0h | R/W-1h | R-0-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-4 | RESERVED | R-0 | 0h | Reserved |
3 | CSA_EN | R/W | 1h | Current Sense Amplifier Enable
0h = Current Sense Amplifier is disabled 1h = Current Sense Amplifier is enabled |
2 | RESERVED | R-0 | 0h | Reserved |
1-0 | CSA_GAIN | R/W | 0h | Current Sense Amplifier Gain settings
0h = CSA gain is 0.25 V/A 1h = CSA gain is 0.5 V/A 2h = CSA gain is 1 V/A 3h = CSA gain is 2 V/A |
SYS_CTRL is shown in #DRV8311_DRV8311_DRV8311_SYS_CTRL_FIGURE and described in #DRV8311_DRV8311_DRV8311_SYS_CTRL_TABLE.
Return to the Summary Table.
System Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Parity_bit | WRITE_KEY | RESERVED | RESERVED | ||||
R-0h | W-0h | R-0-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG_LOCK | SPI_PEN | RESERVED | RESERVED | RESERVED | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Parity_bit | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-12 | WRITE_KEY | W | 0h | 0x5 Write Key Specific to this register. |
11-9 | RESERVED | R-0 | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | REG_LOCK | R/W | 0h | Register Lock Bit
0h = Registers Unlocked 1h = Registers Locked |
6 | SPI_PEN | R/W | 0h | Parity Enable for both SPI and tSPI
0h = Parity Disabled 1h = Parity Enabled |
5-4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2-0 | RESERVED | R/W | 0h | Reserved |