JAJSO55 December 2022 DRV8317
PRODUCTION DATA
After an OCP event in this mode, all the FETs are in Hi-Z and the nFAULT pin is driven low. The FAULT, OCP bits (in DEV_STS register) and corresponding FETs' OCP bits (in DRV_STS register) are set to 1b. Normal operation resumes automatically (pre-driver operation, the nFAULT pin is released and corresponding FETs' OCP bits are set to 1b) after the retry time (tRETRY) time elapses. The FAULT and OCP bits stay set to 1b until clear fault command is issued either through the FLT_CLR bit or an nSLEEP reset pulse (tRST).
Retry time (tRETRY) is set by,