JAJSD42B February   2017  – December 2017 DRV8320 , DRV8320R , DRV8323 , DRV8323R

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 デバイス比較表
  7. 7 ピン構成および機能
    1.     ピン機能rep%#8212;32ピンDRV8320デバイス
    2.     ピン機能rep%#8212;40ピンDRV8320Rデバイス
    3.     ピン機能rep%#8212;40ピンDRV8323デバイス
    4.     ピン機能rep%#8212;48ピンDRV8323Rデバイス
  8. 8 仕様
    1. 8.1 絶対最大定格
    2. 8.2 ESD定格
    3. 8.3 推奨動作条件
    4. 8.4 熱特性
    5. 8.5 電気的特性
    6. 8.6 SPIのタイミング要件
    7. 8.7 代表的特性
  9. 9 詳細説明
    1. 9.1 概要
    2. 9.2 機能ブロック図
    3. 9.3 機能説明
      1. 9.3.1 3相スマート・ゲート・ドライバ
        1. 9.3.1.1 PWM制御モード
          1. 9.3.1.1.1 6x PWMモード（PWM_MODE = 00bまたはMODEピンをAGNDに接続）
          2. 9.3.1.1.2 3x PWMモード（PWM_MODE = 01bまたはMODEピンを47kΩの抵抗を介してAGNDに接続）
          3. 9.3.1.1.3 1x PWMモード（PWM_MODE = 10bまたはMODEピン = Hi-Z）
          4. 9.3.1.1.4 独立PWMモード（PWM_MODE = 11bまたはMODEピンをDVDDに接続）
        2. 9.3.1.2 デバイス・インターフェイス・モード
          1. 9.3.1.2.1 シリアル・ペリフェラル・インターフェイス（SPI）
          2. 9.3.1.2.2 ハードウェア・インターフェイス
        3. 9.3.1.3 ゲート・ドライバ電源電圧
        4. 9.3.1.4 スマート・ゲート・ドライブ・アーキテクチャ
          1. 9.3.1.4.1 IDRIVE：MOSFETスルー・レート制御
          2. 9.3.1.4.2 TDRIVE：MOSFETゲート駆動制御
          3. 9.3.1.4.3 伝搬遅延
          4. 9.3.1.4.4 MOSFET VDS監視
          5. 9.3.1.4.5 VDRAINセンス・ピン
      2. 9.3.2 DVDDリニア電圧レギュレータ
      3. 9.3.3 ピン配置
      4. 9.3.4 ローサイド電流センス・アンプ（DRV8323とDRV8323Rのみ）
        1. 9.3.4.1 双方向電流センスの動作
        2. 9.3.4.2 単方向電流センスの動作（SPIのみ）
        3. 9.3.4.3 自動オフセット較正
        4. 9.3.4.4 MOSFET VDSセンス・モード（SPIのみ）
      5. 9.3.5 降圧型レギュレータ
        1. 9.3.5.1 固定周波数PWM制御
        2. 9.3.5.2 ブートストラップ電圧（CB）
        3. 9.3.5.3 出力電圧設定
        4. 9.3.5.4 nSHDNおよびVIN低電圧誤動作防止のイネーブル
        5. 9.3.5.5 電流制限
        6. 9.3.5.6 過電圧過渡保護
        7. 9.3.5.7 サーマル・シャットダウン
      6. 9.3.6 ゲート・ドライバ保護回路
        1. 9.3.6.1 VM電源の低電圧誤動作防止（UVLO）
        2. 9.3.6.2 VCPチャージ・ポンプの低電圧誤動作防止（CPUV）
        3. 9.3.6.3 MOSFET VDS過電流保護（VDS_OCP）
          1. 9.3.6.3.1 VDSラッチ・シャットダウン（OCP_MODE = 00b）
          2. 9.3.6.3.2 VDS自動リトライ（OCP_MODE = 01b）
          3. 9.3.6.3.3 VDS通知のみ（OCP_MODE = 10b）
          4. 9.3.6.3.4 VDSディスエーブル（OCP_MODE = 11b）
        4. 9.3.6.4 VSENSE過電流保護（SEN_OCP）
          1. 9.3.6.4.1 VSENSEラッチ・シャットダウン（OCP_MODE = 00b）
          2. 9.3.6.4.2 VSENSE自動リトライ（OCP_MODE = 01b）
          3. 9.3.6.4.3 VSENSE通知のみ（OCP_MODE = 10b）
          4. 9.3.6.4.4 VSENSEディスエーブル（OCP_MODE = 11bまたはDIS_SEN = 1b）
        5. 9.3.6.5 ゲート・ドライバ障害（GDF）
        6. 9.3.6.6 過熱警告（OTW）
        7. 9.3.6.7 サーマル・シャットダウン（OTSD）
    4. 9.4 デバイスの機能モード
      1. 9.4.1 ゲート・ドライバの機能モード
        1. 9.4.1.1 スリープ・モード
        2. 9.4.1.2 動作モード
        3. 9.4.1.3 障害リセット（CLR_FLTまたはENABLEリセット・パルス）
      2. 9.4.2 降圧レギュレータの機能モード
        1. 9.4.2.1 連続導通モード（CCM）
        2. 9.4.2.2 Eco-mode制御方式
    5. 9.5 プログラミング
      1. 9.5.1 SPI通信
        1. 9.5.1.1 SPI
          1. 9.5.1.1.1 SPIフォーマット
    6. 9.6 レジスタ・マップ
      1. Table 1. DRV832xSおよびDRV832xRSのレジスタ・マップ
      2. 9.6.1    ステータス・レジスタ
        1. 9.6.1.1 障害ステータス・レジスタ1（アドレス = 0x00）
          1. Table 11. 障害ステータス・レジスタ1のフィールド説明
        2. 9.6.1.2 障害ステータス・レジスタ2（アドレス = 0x01）
          1. Table 12. 障害ステータス・レジスタ2のフィールド説明
      3. 9.6.2    制御レジスタ
        1. 9.6.2.1 ドライバ制御レジスタ（アドレス = 0x02）
          1. Table 14. ドライバ制御のフィールド説明
        2. 9.6.2.2 ゲート駆動HSレジスタ（アドレス = 0x03）
          1. Table 15. ゲート駆動HSのフィールド説明
        3. 9.6.2.3 ゲート駆動LSレジスタ（アドレス = 0x04）
          1. Table 16. ゲート駆動LSレジスタのフィールド説明
        4. 9.6.2.4 OCP制御レジスタ（アドレス = 0x05）
          1. Table 17. OCP制御のフィールド説明
        5. 9.6.2.5 CSA制御レジスタ（DRV8323xのみ）（アドレス = 0x06）
          1. Table 18. CSA制御のフィールド説明
  10. 10アプリケーションと実装
    1. 10.1 アプリケーション情報
    2. 10.2 代表的なアプリケーション
      1. 10.2.1 主要アプリケーション
        1. 10.2.1.1 設計要件
        2. 10.2.1.2 詳細な設計手順
          1. 10.2.1.2.1 外部MOSFETのサポート
            1. 10.2.1.2.1.1 例
          2. 10.2.1.2.2 IDRIVEの設定
            1. 10.2.1.2.2.1 例
          3. 10.2.1.2.3 VDS過電流監視の設定
            1. 10.2.1.2.3.1 例
          4. 10.2.1.2.4 センス・アンプの双方向設定（DRV8323およびDRV8323R）
            1. 10.2.1.2.4.1 例
          5. 10.2.1.2.5 降圧レギュレータの設定（DRV8320RおよびDRV8323R）
        3. 10.2.1.3 アプリケーション曲線
      2. 10.2.2 代替アプリケーション
        1. 10.2.2.1 設計要件
        2. 10.2.2.2 詳細な設計手順
          1. 10.2.2.2.1 センス・アンプの単方向設定
            1. 10.2.2.2.1.1 例
  11. 11電源に関する推奨事項
    1. 11.1 バルク容量の決定
  12. 12レイアウト
    1. 12.1 レイアウトのガイドライン
      1. 12.1.1 降圧レギュレータのレイアウトのガイドライン
    2. 12.2 レイアウト例
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デバイスの項目表記
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 ピン構成および機能

DRV8320H RTV Package
32-Pin WQFN With Exposed Thermal Pad
Top View
DRV8320S RTV Package
32-Pin WQFN With Exposed Thermal Pad
Top View

ピン機能—32ピンDRV8320デバイス

PIN TYPE(1) DESCRIPTION
NAME NO.
DRV8320H DRV8320S
AGND 23 23 PWR Device analog ground. Connect to system ground.
CPH 1 1 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
CPL 32 32 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
DVDD 24 24 PWR 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins. This regulator can source up to 30 mA externally.
ENABLE 22 22 I Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40-µs pulse can be used to reset fault conditions.
GHA 5 5 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 12 12 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 13 13 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 7 7 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 10 10 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 15 15 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
IDRIVE 19 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA 25 25 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 27 27 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 29 29 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 26 26 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 28 28 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 30 30 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE 18 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
NC 21 — NC No internal connection. This pin can be left floating or connected to system ground.
nFAULT 17 17 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS — 21 I Serial chip select. A logic low on this pin enables serial interface communication.
PGND 31 31 PWR Device power ground. Connect to system ground.
SCLK — 20 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI — 19 I Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO — 18 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA 6 6 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 11 11 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 14 14 I High-side source sense input. Connect to the high-side power MOSFET source.
SLA 8 8 I Low-side source sense input. Connect to the low-side power MOSFET source.
SLB 9 9 I Low-side source sense input. Connect to the low-side power MOSFET source.
SLC 16 16 I Low-side source sense input. Connect to the low-side power MOSFET source.
VCP 2 2 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.
VDRAIN 4 4 I High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.
VDS 20 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VM 3 3 PWR Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and PGND pins.
Thermal Pad PWR Must be connected to ground
(1) PWR = 電源、I = 入力、O = 出力、NC = 接続なし、OD = オープン・ドレイン出力
DRV8320RH RHA Package
40-Pin VQFN With Exposed Thermal Pad
Top View
DRV8320RS RHA Package
40-Pin VQFN With Exposed Thermal Pad
Top View

ピン機能—40ピンDRV8320Rデバイス

PIN TYPE(1) DESCRIPTION
NAME NO.
DRV8320RH DRV8320RS
AGND 26 26 PWR Device analog ground. Connect to system ground.
BGND 34 34 PWR Buck regulator ground. Connect to system ground.
CB 35 35 PWR Buck regulator bootstrap input. Connect a X5R or X7R, 0.1-µF, 16-V, capacitor between the CB and SW pins.
CPH 3 3 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
CPL 2 2 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
DVDD 27 27 PWR 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins. This regulator can source up to 30 mA externally.
ENABLE 25 25 I Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions.
FB 40 40 I Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
GHA 7 7 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 14 14 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 15 15 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 9 9 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 12 12 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 17 17 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GND 19 19 PWR Device ground. Connect to system ground.
IDRIVE 22 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA 28 28 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 30 30 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 32 32 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 29 29 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 31 31 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 33 33 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE 21 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
NC 24 — NC No internal connection. This pin can be left floating or connected to system ground.
NC 37 37 NC No internal connection. This pin can be left floating or connected to system ground.
nFAULT 20 20 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS — 24 I Serial chip select. A logic low on this pin enables serial interface communication.
nSHDN 39 39 I Buck shutdown input. Enable and disable input (high voltage tolerant). Internal pullup current source. Pull lower than 1.25 V to disable. Float to enable. Establish input undervoltage lockout with two resistor divider.
PGND 1 1 PWR Device power ground. Connect to system ground.
SCLK — 23 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI — 22 I Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO — 21 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA 8 8 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 13 13 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 16 16 I High-side source sense input. Connect to the high-side power MOSFET source.
SLA 10 10 I Low-side source sense input. Connect to the low-side power MOSFET source.
SLB 11 11 I Low-side source sense input. Connect to the low-side power MOSFET source.
SLC 18 18 I Low-side source sense input. Connect to the low-side power MOSFET source.
SW 36 36 O Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
VCP 4 4 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.
VDRAIN 6 6 I High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.
VDS 23 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VIN 38 38 PWR Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins.
VM 5 5 PWR Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and PGND pins.
Thermal Pad PWR Must be connected to ground
(1) PWR = 電源、I = 入力、O = 出力、NC = 接続なし、OD = オープン・ドレイン出力
DRV8323H RTA Package
40-Pin WQFN With Exposed Thermal Pad
Top View
DRV8323S RTA Package
40-Pin WQFN With Exposed Thermal Pad
Top View

ピン機能—40ピンDRV8323デバイス

PIN TYPE(1) DESCRIPTION
NAME NO.
DRV8323H DRV8323S
AGND 32 32 PWR Device analog ground. Connect to system ground.
CAL 31 31 I Amplifier calibration input. Set logic high to internally short amplifier inputs and perform auto offset calibration.
CPH 2 2 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
CPL 1 1 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
DVDD 33 33 PWR R 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins. This regulator can source up to 30 mA externally.
ENABLE 30 30 I Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions.
GAIN 29 — I Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GHA 6 6 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 15 15 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 16 16 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 8 8 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 13 13 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 18 18 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
IDRIVE 27 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA 34 34 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 36 36 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 38 38 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 35 35 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 37 37 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 39 39 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE 26 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
nFAULT 25 25 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS — 29 I Serial chip select. A logic low on this pin enables serial interface communication.
PGND 40 40 PWR Device power ground. Connect to system ground.
SCLK — 28 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI — 27 I Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO — 26 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA 7 7 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 14 14 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 17 17 I High-side source sense input. Connect to the high-side power MOSFET source.
SNA 10 10 I Current sense amplifier input. Connect to the low-side of the current shunt resistor.
SNB 11 11 I Current sense amplifier input. Connect to the low-side of the current shunt resistor.
SNC 20 20 I Current sense amplifier input. Connect to the low-side of the current shunt resistor.
SOA 23 23 O Current sense amplifier output.
SOB 22 22 O Current sense amplifier output.
SOC 21 21 O Current sense amplifier output.
SPA 9 9 I Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPB 12 12 I Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPC 19 19 I Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
VCP 3 3 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.
VDRAIN 5 5 I High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.
VDS 28 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VM 4 4 PWR Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and PGND pins.
VREF 24 24 PWR Current sense amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins.
Thermal Pad PWR Must be connected to ground
(1) PWR = 電源、I = 入力、O = 出力、NC = 接続なし、OD = オープン・ドレイン出力
DRV8323RH RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
DRV8323RS RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View

ピン機能—48ピンDRV8323Rデバイス

PIN TYPE(1) DESCRIPTION
NAME NO.
DRV8323RH DRV8323RS
AGND 35 35 PWR Device analog ground. Connect to system ground.
BGND 43 43 PWR Buck regulator ground. Connect to system ground.
CAL 34 34 I Amplifier calibration input. Set logic high to internally short amplifier inputs and perform auto offset calibration.
CB 44 44 PWR Buck regulator bootstrap input. Connect a X5R or X7R, 0.1-µF, 16-V, capacitor between the CB and SW pins.
CPH 4 4 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
CPL 3 3 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
DGND 27 27 PWR Device ground. Connect to system ground.
DVDD 36 36 PWR 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins. This regulator can source up to 30 mA externally.
ENABLE 33 33 I Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions.
FB 1 1 I Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
GAIN 32 — I Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GHA 8 8 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 17 17 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 18 18 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 10 10 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 15 15 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 20 20 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
IDRIVE 30 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA 37 37 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 39 39 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 41 41 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 38 38 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 40 40 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 42 42 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE 29 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
NC 46 46 NC No internal connection. This pin can be left floating or connected to system ground.
nFAULT 28 28 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS — 32 I Serial chip select. A logic low on this pin enables serial interface communication.
nSHDN 48 48 I Buck shutdown input. Enable and disable input (high voltage tolerant). Internal pullup current source. Pull lower than 1.25 V to disable. Float to enable. Establish input undervoltage lockout with two resistor divider.
PGND 2 2 PWR Device power ground. Connect to system ground.
SCLK — 31 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI — 30 I Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO — 29 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA 9 9 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 16 16 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 19 19 I High-side source sense input. Connect to the high-side power MOSFET source.
SNA 12 12 I Current sense amplifier input. Connect to the low-side of the current shunt resistor.
SNB 13 13 I Current sense amplifier input. Connect to the low-side of the current shunt resistor.
SNC 22 22 I Current sense amplifier input. Connect to the low-side of the current shunt resistor.
SOA 25 25 O Current sense amplifier output.
SOB 24 24 O Current sense amplifier output.
SOC 23 23 O Current sense amplifier output.
SPA 11 11 I Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPB 14 14 I Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPC 21 21 I Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SW 45 45 O Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
VCP 5 5 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.
VDRAIN 7 7 I High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.
VDS 31 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VIN 47 47 PWR Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins.
VM 6 6 PWR Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and PGND pins.
VREF 26 26 PWR Current sense amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins.
Thermal Pad PWR Must be connected to ground
(1) PWR = 電源、I = 入力、O = 出力、NC = 接続なし、OD = オープン・ドレイン出力