JAJSOU0A June   2022  – October 2022 DRV8329

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specification
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings Comm
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information 1pkg
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three BLDC Gate Drivers
        1. 8.3.1.1 PWM Control Modes
          1. 8.3.1.1.1 6x PWM Mode
          2. 8.3.1.1.2 3x PWM Mode
        2. 8.3.1.2 Device Hardware Interface
        3. 8.3.1.3 Gate Drive Architecture
          1. 8.3.1.3.1 Propagation Delay
          2. 8.3.1.3.2 Deadtime and Cross-Conduction Prevention
      2. 8.3.2 AVDD Linear Voltage Regulator
      3. 8.3.3 Pin Diagrams
      4. 8.3.4 Low-Side Current Sense Amplifiers
        1. 8.3.4.1 Current Sense Operation
      5. 8.3.5 Gate Driver Shutdown Sequence (DRVOFF)
      6. 8.3.6 Gate Driver Protective Circuits
        1. 8.3.6.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 8.3.6.2 AVDD Power on Reset (AVDD_POR)
        3. 8.3.6.3 GVDD Undervoltage Lockout (GVDD_UV)
        4. 8.3.6.4 BST Undervoltage Lockout (BST_UV)
        5. 8.3.6.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 8.3.6.6 VSENSE Overcurrent Protection (SEN_OCP)
        7. 8.3.6.7 Thermal Shutdown (OTSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Gate Driver Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (nSLEEP Reset Pulse)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Three Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1  Motor Voltage
          2. 9.2.1.1.2  Bootstrap Capacitor and GVDD Capacitor Selection
          3. 9.2.1.1.3  Gate Drive Current
          4. 9.2.1.1.4  Gate Resistor Selection
          5. 9.2.1.1.5  System Considerations in High Power Designs
            1. 9.2.1.1.5.1 Capacitor Voltage Ratings
            2. 9.2.1.1.5.2 External Power Stage Components
            3. 9.2.1.1.5.3 Parallel MOSFET Configuration
          6. 9.2.1.1.6  Dead Time Resistor Selection
          7. 9.2.1.1.7  VDSLVL Selection
          8. 9.2.1.1.8  AVDD Power Losses
          9. 9.2.1.1.9  Current Sensing and Output Filtering
          10. 9.2.1.1.10 Power Dissipation and Junction Temperature Losses
      2. 9.2.2 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

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発注情報

6 Pin Configuration and Functions

Figure 6-1 DRV8329 REE Package36-pin VQFN With Exposed Thermal PadTop View
Table 6-1 Pin Functions—36-Pin DRV8329 Devices
NAMEPIN NO.TYPEDESCRIPTION
DRV8329
AGND 25 PWR Device analog ground. Refer Section 11.1 for the recommendation on connection.
AVDD26PWR-O3.3-V regulator output. Connect a X5R or X7R, 1-µF, >6.3-V ceramic capacitor between the AVDD and GND pins. This regulator can source up to 80 mA externally. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin.
BSTA9OBootstrap output pin. Connect a X5R or X7R, 1-µF, 25-V ceramic capacitor between BSTA and SHA
BSTB13OBootstrap output pin. Connect a X5R or X7R, 1-µF, 25-V ceramic capacitor between BSTB and SHB
BSTC17OBootstrap output pin. Connect a X5R or X7R, 1-µF, 25-V ceramic capacitor between BSTC and SHC
CSAGAIN33IGain settings for Current sense amplifier. The pin is a 4 level input pin set by an external resistor. See Section 8.3.4 for more information.
CSAREF1ICurrent sense amplifier reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the CSAREF and AGND pins.
CPH7PWRCharge pump switching node. Connect a X5R or X7R, PVDD-rated ceramic capacitor between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin.
CPL6PWR
DRVOFF24IIndependent driver shutdown path. Pulling DRVOFF high turns off all external MOSFETs by putting the gate drivers into the pull-down state. This signal bypasses and overrides the digital core of DRV8329.
DT3IGate drive deadtime setting. Connect a resistor of value between 10 kΩ to 390 kΩ between DT and GND to adjust deadtime between 100 ns to 2000 ns. If pin is left floating or connected to GND fixed value of 55 ns deadtime is inserted.
GHA11OHigh-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB15OHigh-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC19OHigh-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA12OLow-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB16OLow-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC20OLow-side gate driver output. Connect to the gate of the low-side power MOSFET.
GVDD8PWR-OGate driver power supply output. Connect a X5R or X7R, 30-V rated ceramic ≥ 10-uF local capacitance between the GVDD and GND pins. TI recommends a capacitor value of >10x CBSTx and voltage rating at least twice the normal operating voltage of the pin.
GND4PWRDevice ground. Refer Section 11.1 for the recommendation on connection.
INHA29IHigh-side gate driver control input for Phase A. This pin controls the output of the high-side FET.
INHB28IHigh-side gate driver control input for Phase B. This pin controls the output of the high-side FET.
INHC27IHigh-side gate driver control input for Phase C. This pin controls the output of the high-side FET.
INLA32ILow-side gate driver control input for Phase A. This pin controls the output of the low-side FET.
INLB31ILow-side gate driver control input for Phase B. This pin controls the output of the low-side FET.
INLC30ILow-side gate driver control input for Phase C. This pin controls the output of the low-side FET.
LSS21PWRLow side source pin, connect all sources of the external low-side MOSFETs here. This pin is the sink path for the low-side gate driver, and serves as an input to monitor the low-side MOSFET VDS voltage and VSEN_OCP voltage.
nFAULT35ODFault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor to 3.3V to 5.0V.
nSLEEP34ISleep mode entry pin. When this pin is pulled logic low the device goes to a low-power sleep mode. An 1 to 1.2-µs low pulse can be used to reset fault conditions without entering sleep mode.
PVDD5PWRGate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, >2x PVDD-rated ceramic and >10-uF local capacitance between the PVDD and GND pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin.
SHA10I/OHigh-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink.
SHB14I/OHigh-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink.
SHC18I/OHigh-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink.
SO2OCurrent sense amplifier output. Supports capacitive load or low pass filter (resistor in series and capacitor to GND)
SP22ICurrent shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SN23ICurrent sense amplifier input. Connect to the low-side of the current shunt resistor.
VDSLVL36IVDS monitor trip point setting. Connect an analog level input from 0.1 V to 2.5 V to set a VDS monitor trip point setting for MOSFET overcurrent protection. See Section 9.2.1.1.7 for more information.
Thermal PadPWRMust be connected to GND