JAJSOU0A June   2022  – October 2022 DRV8329

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specification
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings Comm
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information 1pkg
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three BLDC Gate Drivers
        1. 8.3.1.1 PWM Control Modes
          1. 8.3.1.1.1 6x PWM Mode
          2. 8.3.1.1.2 3x PWM Mode
        2. 8.3.1.2 Device Hardware Interface
        3. 8.3.1.3 Gate Drive Architecture
          1. 8.3.1.3.1 Propagation Delay
          2. 8.3.1.3.2 Deadtime and Cross-Conduction Prevention
      2. 8.3.2 AVDD Linear Voltage Regulator
      3. 8.3.3 Pin Diagrams
      4. 8.3.4 Low-Side Current Sense Amplifiers
        1. 8.3.4.1 Current Sense Operation
      5. 8.3.5 Gate Driver Shutdown Sequence (DRVOFF)
      6. 8.3.6 Gate Driver Protective Circuits
        1. 8.3.6.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 8.3.6.2 AVDD Power on Reset (AVDD_POR)
        3. 8.3.6.3 GVDD Undervoltage Lockout (GVDD_UV)
        4. 8.3.6.4 BST Undervoltage Lockout (BST_UV)
        5. 8.3.6.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 8.3.6.6 VSENSE Overcurrent Protection (SEN_OCP)
        7. 8.3.6.7 Thermal Shutdown (OTSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Gate Driver Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (nSLEEP Reset Pulse)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Three Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1  Motor Voltage
          2. 9.2.1.1.2  Bootstrap Capacitor and GVDD Capacitor Selection
          3. 9.2.1.1.3  Gate Drive Current
          4. 9.2.1.1.4  Gate Resistor Selection
          5. 9.2.1.1.5  System Considerations in High Power Designs
            1. 9.2.1.1.5.1 Capacitor Voltage Ratings
            2. 9.2.1.1.5.2 External Power Stage Components
            3. 9.2.1.1.5.3 Parallel MOSFET Configuration
          6. 9.2.1.1.6  Dead Time Resistor Selection
          7. 9.2.1.1.7  VDSLVL Selection
          8. 9.2.1.1.8  AVDD Power Losses
          9. 9.2.1.1.9  Current Sensing and Output Filtering
          10. 9.2.1.1.10 Power Dissipation and Junction Temperature Losses
      2. 9.2.2 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout Guidelines

Bypass the PVDD pin to the PGND pin using a low-ESR ceramic bypass capacitor with a recommended value of 0.1 µF. Place this capacitor as close to the PVDD pin as possible with a thick trace or ground plane connected to the PGND pin. Additionally, bypass the PVDD pin using a bulk capacitor rated for PVDD. This component can be electrolytic. This capacitance must be at least 10 µF.

Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk capacitance should be placed such that it minimizes the length of any high current paths through the external MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB layers. These practices minimize inductance and let the bulk capacitor deliver high current.

Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 470 nF, rated for PVDD, and be of type X5R or X7R.

The bootstrap capacitors (BSTx-SHx) should be placed closely to device pins to minimize loop inductance for the gate drive paths.

The dead time resistor (RDT) should be placed as close as possible to the DT pin.

Bypass the AVDD pin to the AGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type X5R or X7R. Place this capacitor as close to the pin as possible and minimize the path from the capacitor to the AGND pin.

Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the low-side MOSFET source back to the PGND pin.

When designing higher power systems, physics in the PCB layout can cause parasitic inductances, capacitances, and impedances that deter the performance of the system as shown in Figure 11-1. Understanding the parasitics that are present in a higher power motor drive system can help designers mitigate their effects through good PCB layout. For more information, please visit the System Design Considerations for High-Power Motor Driver Applications and Best Practices for Board Layout of Motor Drivers application notes.

Figure 11-1 Parasitics in the PCB of a BLDC motor driver powerstage

Gate drive traces (BSTx, GHx, SHx, GLx, LSS) should be at least 15-20mil wide and as short as possible to the MOSFET gates to minimize parasitic inductances and impedances. This helps supply large gate drive currents, turn MOSFETs on efficiently, and improves VGS and VDS monitoring. If a shunt resistor is used to monitor the low-side current from LSS to GND, ensure the shunt resistor selected is wide to minimize inductance introduced at the low-side source LSS.

TI recommends connecting all non-power stage circuitry (including the thermal pad) to GND to reduce parasitic effects and improve power dissipation from the device. Ensure grounds are connected through net-ties or wide resistors to reduce voltage offsets and maintain gate driver performance.

The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate the heat that is generated in the device.

To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and improve thermal dissipation from the die surface.