JAJSHI4 May 2019 DRV8340-Q1
PRODUCTION DATA.
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
tREADY | SPI ready after enable | VM > UVLO, ENABLE = 3.3 V | 1 | ms | ||
tCLK | SCLK minimum period | 100 | ns | |||
tCLKH | SCLK minimum high time | 50 | ns | |||
tCLKL | SCLK minimum low time | 50 | ns | |||
tSU_SDI | SDI input data setup time | 20 | ns | |||
tH_SDI | SDI input data hold time | 30 | ns | |||
tD_SDO | SDO output data delay time | SCLK high to SDO valid, CL = 20 pF | 30 | ns | ||
tSU_nSCS | nSCS input setup time | 50 | ns | |||
tH_nSCS | nSCS input hold time | 50 | ns | |||
tHI_nSCS | nSCS minimum high time before active low | 500 | ns | |||
tDIS_nSCS | nSCS disable time | nSCS high to SDO high impedance | 10 | ns |