JAJSHI4 May 2019 DRV8340-Q1
PRODUCTION DATA.
If at any time the input supply voltage on the VM pin falls lower than the VUVLO threshold, all of the external MOSFETs are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The FAULT and VM_UVLO bits are also latched high in the registers on SPI devices. Normal operation starts again (gate driver operation and the nFAULT pin is released) when the VM undervoltage condition clears. The VM_UVLO bit stays set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST).