JAJSHI4 May 2019 DRV8340-Q1
PRODUCTION DATA.
In latched shutdown mode, after a OTSD event, normal operation starts again (motor driver operation and the nFAULT line released) when the OTSD condition is removed and a clear faults command has been issued either through the CLR_FLT bit or an nSLEEP reset pulse. This is the default mode for a OTSD event in the SPI device.
When the DRV8340-Q1 device hits thermal shutdown, the OTSD and FAULT bits are latched in the SPI register. Clearing the fault through the CLR_FLT bit or an nSLEEP reset pulse will clear the OSTD and FAULT bits. When the DRV8340-Q1 device hits thermal shutdown, the device will disable the charge pump without triggering CPUV. The charge pump will be enabled again when the OTSD and FAULT bits are cleared through the CLR_FLT bit or an nSleep reset Pulse.