JAJSHI4 May 2019 DRV8340-Q1
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
GATE DRIVER | ||||
Power supply pin voltage (VM) | –0.3 | 65 | V | |
Voltage differential between ground pins (AGND, BGND, DGND, PGND) | –0.3 | 0.3 | V | |
MOSFET drain sense pin voltage (VDRAIN) | –0.3 | 65 | V | |
Charge pump pin voltage (CPH, VCP) | –0.3 | VVM + 13.5 | V | |
Charge-pump negative-switching pin voltage (CPL) | –0.3 | VVM | V | |
Internal logic regulator pin voltage (DVDD) | –0.3 | 3.8 | V | |
Voltage difference between VM and VDRAIN | –10 | 10 | V | |
Digital pin voltage (ENABLE, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO, VDS, nDIAG) | –0.3 | 5.75 | V | |
Continuous high-side gate drive pin voltage (GHx) | –5(2) | VVCP + 0.5 | V | |
Transient 200-ns high-side gate drive pin voltage (GHx) | –7 | VVCP + 0.5 | V | |
High-side gate drive pin voltage with respect to SHx (GHx) | –0.3 | 13.5 | V | |
Continuous high-side source sense pin voltage (SHx, DLx) | –5(2) | VVM + 5 | V | |
Transient 200-ns high-side source sense pin voltage (SHx, DLx) | –7 | VVM + 7 | V | |
Continuous high-side source sense pin voltage (SHx, DLx) | –5(2) | VDRAIN + 5 | V | |
Transient 200-ns high-side source sense pin voltage (SHx, DLx) | –7 | VDRAIN + 7 | V | |
Continuous low-side gate drive pin voltage (GLx) | –0.5 | 15 | V | |
Gate drive pin source current (GHx, GLx) | Internally limited | A | ||
Gate drive pin sink current (GHx, GLx) | Internally limited | A | ||
Continuous low-side source sense pin voltage (SLx) | –1 | 1 | V | |
Transient 200-ns low-side source sense pin voltage (SLx) | –3 | 3 | V | |
Push-pull output buffer reference voltage (VSDO) | –0.3 | 5.75 | V | |
Push-pull output current (SDO) | 0 | 10 | mA | |
Open drain pullup voltage (nFAULT) | –0.3 | 5.75 | V | |
Open drain output current (nFAULT) | 0 | 10 | mA | |
Operating junction temperature, TJ | –40 | 150 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |