JAJSVI5 October   2024 DRV8376

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Slave Mode Timings
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Control Modes
        1. 7.3.2.1 6x PWM Mode (PWM_MODE = 00b or 01b or MODE_SR Pin Tied to AGND or in Hi-Z)
        2. 7.3.2.2 3x PWM Mode (xPWM_MODE = 10b or 11b or MODE_SR Pin is Connected to GVDD or to GVDD with RMODE)
      3. 7.3.3  Device Interface Modes
        1. 7.3.3.1 Serial Peripheral Interface (SPI)
        2. 7.3.3.2 Hardware Interface
      4. 7.3.4  AVDD and GVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Propagation Delay
      9. 7.3.9  Pin Diagrams
        1. 7.3.9.1 Logic Level Input Pin (Internal Pulldown)
        2. 7.3.9.2 Logic Level Input Pin (Internal Pullup)
        3. 7.3.9.3 Open Drain Pin
        4. 7.3.9.4 Push Pull Pin
        5. 7.3.9.5 Four Level Input Pin
      10. 7.3.10 Current Sense Amplifiers
        1. 7.3.10.1 Current Sense Amplifier Operation
      11. 7.3.11 Active Demagnetization
        1. 7.3.11.1 Automatic Synchronous Rectification Mode (ASR Mode)
          1. 7.3.11.1.1 Automatic Synchronous Rectification in Commutation
          2. 7.3.11.1.2 Automatic Synchronous Rectification in PWM Mode
        2. 7.3.11.2 Automatic Asynchronous Rectification Mode (AAR Mode)
      12. 7.3.12 Cycle-by-Cycle Current Limit
        1. 7.3.12.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
      13. 7.3.13 Protections
        1. 7.3.13.1 VM Supply Undervoltage Lockout (RESET)
        2. 7.3.13.2 AVDD Undervoltage Protection (AVDD_UV)
        3. 7.3.13.3 GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.13.4 VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.13.5 Overvoltage Protections (OV)
        6. 7.3.13.6 Overcurrent Protection (OCP)
          1. 7.3.13.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.13.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.13.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.13.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 7.3.13.7 Thermal Warning (OTW)
        8. 7.3.13.8 Thermal Shutdown (OTS)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
      2. 7.4.2 DRVOFF functionality
    5. 7.5 SPI Communication
      1. 7.5.1 Programming
        1. 7.5.1.1 SPI Format
    6. 7.6 Register Map
      1. 7.6.1 STATUS Registers
      2. 7.6.2 CONTROL Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Power Supply Recommendations
      1. 8.2.1 Bulk Capacitance
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
      3. 8.3.3 Thermal Considerations
        1. 8.3.3.1 Power Dissipation
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • NLG|28
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DRV8376 DRV837628-Pin VQFN With Exposed Thermal PadTop ViewFigure 5-1 DRV837628-Pin VQFN With Exposed Thermal PadTop View
Table 5-1 DRV8376 Pin Functions
PIN28-pin VQFN PackageTYPE(1)DESCRIPTION
NAMEDRV8376HDRV8376S
AGND88GNDDevice analog ground. Refer Section 8.3.1 for connections recommendation.
AVDD99PWR O3.3V internal regulator output. Connect an X5R or X7R, 0.1µF, 6.3V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 30mA externally.
CP11PWR OCharge pump output. Connect a X5R or X7R, 0.1µF, 16V ceramic capacitor between the CP and VM pins.
DRVOFF1111IWhen this pin is pulled high the six MOSFETs in the power stage are turned OFF making all outputs Hi-Z.
GAIN21-ICurrent sense amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GVDD1010PWR O5V internal regulator output. Connect an X5R or X7R, 1µF, 10V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 30 mA externally.
ILIMIT2828 Sets the threshold for phase current used in cycle by cycle current limit.
INHA1414IHigh-side driver control input for OUTA. This pin controls the output of the high-side MOSFET.
INHB1616IHigh-side driver control input for OUTB. This pin controls the output of the high-side MOSFET.
INHC1818IHigh-side driver control input for OUTC. This pin controls the output of the high-side MOSFET.
INLA1515ILow-side driver control input for OUTA. This pin controls the output of the low-side MOSFET.
INLB1717ILow-side driver control input for OUTB. This pin controls the output of the low-side MOSFET.
INLC1919ILow-side driver control input for OUTC. This pin controls the output of the low-side MOSFET.
MODE_SR20-IPWM input mode setting. This pin is a 4-level input pin set by an external resistor.
nFAULT1212OFault indicator. Pulled logic-low with fault condition; Open-drain output requires an external pull-up resistor to 1.8V to 5.0V. If an external supply is used to pull up nFAULT, ensure that it is pulled to >2.2V on power up.
nSCS-23ISerial chip select. A logic low on this pin enables serial interface communication.
nSLEEP1313IDriver nSLEEP. When this pin is logic-low, the device goes into a low-power sleep mode. A 20 to 40µs low pulse can be used to reset fault conditions without entering sleep mode.
OCP23-IOCP level setting. This pin is a 2 level input pin set by an external resistor (Hardware devices).
OUTA44PWR OHalf bridge output A
OUTB55PWR OHalf bridge output B
OUTC66PWR OHalf bridge output C
PGND3, 73, 7GNDDevice power ground. Refer Section 8.3.1 for connections recommendation.
SCLK-22ISerial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin (SPI devices).
SDI-21ISerial data input. Data is captured on the falling edge of the SCLK pin (SPI devices).
SDO-20OSerial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor (SPI devices).
SLEW22-ISlew rate control setting. This pin is a 4-level input pin set by an external resistor.
SOA2727OCurrent sense amplifier output. Supports capacitive load or low pass filter (resistor in series and capacitor to GND)
SOB2626OCurrent sense amplifier output. Supports capacitive load or low pass filter (resistor in series and capacitor to GND)
SOC2525OCurrent sense amplifier output. Supports capacitive load or low pass filter (resistor in series and capacitor to GND)
VM22PWR IPower supply. Connect to motor supply voltage; bypass to PGND with a 0.1-µF capacitor plus one bulk capacitor rated for VM. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device.
VREF2424PWR/ICurrent sense amplifier reference. Connect a X5R or X7R, 0.1µF, 6.3V ceramic capacitor between the VREF and AGND pins.
Thermal padAGNDMust be connected to analog ground.
(1) I = input, O = output, GND = ground pin, PWR = power, NC = no connect